tag: packaging

Making It Differently
By Ed Sperling - 02 Apr, 2015 - Comments: 0

Anyone who hasn't bought into the IoT/E as a fundamental shift in electronics should check out what's happening in China. All appliances and electronics being developed for the home market are now being sold as smart-ready. This is a market that comprises roughly one-fifth (19.4% to be exact) of the world's population. In the future, whether or not you hook up a new washing machine or TV to ... » read more

Package Modeling Needs For A Robust IC Power Integrity Sign-Off
By Chris Ortiz - 12 Mar, 2015 - Comments: 0

Progress in IC technology has allowed chip designers to pack more functionality and continually make better use of silicon area. This trend, coupled with the need to maintain low power using techniques such as voltage islands and power and clock gating, has caused the power consumption to vary across the chip and over time. This has introduced considerable amount of transient current peaks in t... » read more

Manufacturing And Packaging Changes For 2015
By Brian Bailey - 22 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

From Specification To Chip: A Holistic Design Approach
By Kalpesh Sanghvi - 18 Dec, 2014 - Comments: 0

Chip design is getting more and more challenging in terms of power, performance, area and IP integration. At the same time, competition and time-to-market are forcing much tighter schedules. The traditional ASIC design approach taken by OEMs is to handle the majority of front-end design in-house, and then hand off either register-transfer level (RTL) code or a netlist to an outside vendor, who ... » read more

Smart Early ASIC Design Prototyping And Analysis
By Sankar Ramachandran - 04 Dec, 2014 - Comments: 0

The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

More Than Moore
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

IoT Growing Pains
By Ed Sperling - 04 Sep, 2014 - Comments: 0

The Internet of Things is having one of those defining moments — and not in a good way. Only a limited number of things will work together at first. Only in rare case will they actually cross boundaries between vertical markets such as consumer or home, automotive and medical. And in no cases will there be any guarantees, at least in the short term, that communications will be reliable, secur... » read more

Ready To Pounce
By Ed Sperling - 21 Aug, 2014 - Comments: 0

A series of inflection points at 16/14nm and beyond is having a rather unusual effect on the semiconductor industry. Rather than forge ahead with the next nodes to gain an edge and early lead over rivals—the standard formula for success over the past five decades—the entire supply chain is poised on the edge, waiting for someone to make the first move before they take action. The problem... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Foundries Versus OSATs
By Ed Sperling - 24 Jul, 2014 - Comments: 2

Since the 1990s, commercial foundries have ruled semiconductor manufacturing while the [getkc id='83' comment='OSAT'] providers (OSATs) have dominated IC packaging and testing. But as the industry moves toward stacked die over the next couple of years, and big foundries see a chance to expand their reach, the stage is set for an all-out war. There is much at stake on both sides. Foundries g... » read more

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