Tech Talk: Configurable Logic


Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

Executive Insight: Lip-Bu Tan


Lip-Bu Tan, president and CEO of Cadence, sat down with Semiconductor Engineering to talk about consolidation, Moore's Law, and where the opportunities are in the IoT and automotive markets. What follows are excerpts of that conversation. SE: What are the big concerns for the semiconductor industry in general, and EDA in particular? Tan: Top on my list is all the consolidation that's goin... » read more

EDA, IP Numbers Up


EDA and IP numbers increased another 8.5% in Q2, with all regions but Japan showing positive growth. Total revenue was $1.91 billion for the quarter, up from $1.76 billion in Q2 of 2014. The largest category, computer-aided engineering, was $657.2 million for the quarter, up 9.6% compared with the same period last year. IC physical design was $379.2 million, up 6% year over year, and IP was ... » read more

Is The 2.5D Supply Chain Ready?


A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

SEMICON Taiwan’s Packaging Punch


SEMICON Taiwan packed a punch, setting several new records and new heights in 2015. This year marked the 20th anniversary of SEMICON in Taiwan and was the largest SEMICON in Taiwan ever, with a Nobel Prize winner (Professor Shuji Nakamura, 2014’s winner) keynoting the Executive Summit, Taiwan’s President Ma speaking at the hugely attended Gala Dinner, and 2015 on track for TSMC to be the wo... » read more

New System Requirements Demand a Creatively Choreographed Ecosystem


In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically. New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to c... » read more

Advanced IC Packaging Biz Heats Up


After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up. On one front, for example, a new wave of chips based on advanced [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP... » read more

IP Market Shifts Direction


Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

What’s Different At 16/14nm?


Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

FD-SOI Vs. FinFETs


Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

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