Improving Parasitic Capacitance In Next-Generation DRAM Devices

By Dempsey Deng - 15 Aug, 2024 - Comments: 0

As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance. New DRAM structures may be needed in the future, to lower total capacitance and achieve acceptable device performance. In this study, we compare the parasitic capacitance of a 6F2 honeycomb dynamic random-access memory (DRAM) device to the parasitic... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance

By Pradeep Nanja - 18 May, 2023 - Comments: 0

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes

By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL

By Sumant Sarkar - 17 Nov, 2022 - Comments: 0

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance

By Taeyon (TY) Oh - 03 Feb, 2020 - Comments: 0

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations

By Jacky Huang - 25 Sep, 2019 - Comments: 0

By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps

By Michael Hargrove - 19 Oct, 2017 - Comments: 0

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been ... » read more

Uncertainty Grows For 5nm, 3nm

By Mark LaPedus - 19 Dec, 2016 - Comments: 4

As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena. [getentity id="22586" comment="TSMC"] recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, whic... » read more

Fins And Wires – How Do We Get To 5nm?

By Mike Chudzik - 18 Aug, 2016 - Comments: 0

As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?