tag: parasitic extraction

How To Get Accurate Inductance Extraction For Superconductor ICs
By Hossam Sarhan - 11 Apr, 2024 - Comments: 0

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and cloud computing requires powerful and efficient integrated circuits (ICs). More semiconductor companies are considering superconductor ICs for their unique properties that allow ultrafast processing of digital information. These properties include fa... » read more

Why Curvy Design Now? Less Change Than You Think And Manufacturable Today
By Jan Willis - 19 Oct, 2023 - Comments: 0

A curvilinear (curvy) chip, if magically made possible, would be smaller, faster, and use less power. Magic is no longer needed on the manufacturing side, as companies like Micron Technology are making photomasks with curvy shapes using state-of-the-art multi-beam mask writers today. Yet the entire chip-design infrastructure is based on the Manhattan assumption of 90-degree turns, even though i... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?
By Karen Chow - 12 Oct, 2023 - Comments: 0

By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

The Value Of Field Solvers In Semiconductor Development Helps Drive Infineon Innovation
By Siemens EDA - 11 Oct, 2023 - Comments: 0

Parasitic extraction (PEX) helps ensure accurate circuit performance in the design and verification flow. Development of accurate PEX runsets depends on accurate and precise extraction results obtained using a full-featured field solver. Infineon selected the Calibre xACT 3D tool as their reference field solver tool of choice in the development of their next-generation semiconductor power produ... » read more

Using Virtual Metal Fill To Predict The Impact Of High Level Nets
By Vamsi Thatha - 14 Sep, 2023 - Comments: 0

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

High-Performance 5G IC Designs Need High-Performance Parasitic Extraction
By Karen Chow - 23 Jun, 2022 - Comments: 0

By Karen Chow and Salma Ahmed Elhenedy We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does that mean for the average person? Think about cellphones, for one. You don't just use your phone for calling or texting anymore—you surf the web, chec... » read more

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Is Common Resistance Affecting Your Analog Design Reliability And Performance?
By Hossam Sarhan - 11 Jun, 2020 - Comments: 0

Integrated circuit (IC) design reliability has always been important and essential to market success. After all, if no one could count on your product to operate as designed, and for as long as intended, there wouldn’t be many buyers! However, given the increase in the types and complexity of design applications, coupled with the increasing technological challenge of manufacturing at advance... » read more

Parasitic Extraction of MIM/MOM Capacitors In Analog/RF Designs
By Mentor, a Siemens Business - 26 Feb, 2020 - Comments: 0

The extensive use of MIM/MOM capacitors in analog/RF designs presents designers with extraction challenges that typically require multiple extraction techniques. The Calibre xACT platform offers analog/RF designers the fast performance of a rule-based extraction engine, and the capacity and performance of a field solver, to efficiently extract all parasitic components in a timely manner, with t... » read more

New Parasitic Extraction Requirements In Custom Design For The Next Wave Of SoCs
By Ash Patel - 30 Jan, 2020 - Comments: 0

Fast growing markets like 5G, biotechnology, AI, and automotive are driving the new wave in semiconductor design and the need for highly integrated system on chip (SoCs). Power management, sensors, RF and precision analog functionality are all integrated on the same substrate which poses new challenges for custom design tools. Specifically, there are new challenges for parasitic extraction that... » read more

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