What Machine Learning Can Do In Fabs

By Mark LaPedus - 25 Mar, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. L-R:... » read more

Improving Circuit Reliability

By Ed Sperling - 03 Mar, 2020 - Comments: 0

Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving growing concern about the reliability and fidelity of analog circuits, and the impact of running circuits for longer periods of time under different voltage and environmental conditions. » read more

Balancing Flexibility And Quality In SRAM Verification

By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Where ML Works Best

By Ed Sperling - 26 Jul, 2018 - Comments: 0

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to discuss machine learning inside and outside of EDA tools and how that will affect the future of chip and system design. What follows are excerpts of that discussion. SE: How do you see the market and use of machine learning shaping up? Devgan: There are three main areas—machine learning inside, machine lear... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm

By Cadence - 24 Jan, 2018 - Comments: 0

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

Blog Review: Dec. 13

By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

SRAM Physical Verification With Calibre Pattern Matching

By Mentor, a Siemens Business - 14 Dec, 2016 - Comments: 0

Traditional SRAM verification flows can require significant resources to implement and support, and still miss critical errors that result in manufacturing defects. Using the Calibre Pattern Matching automated pattern-based solution provides accurate results, avoids costly mask re-spins, and is easily updated to add newly developed SRAM IP cells. To read more, click here. » read more

Pattern Matching In Test And Yield Analysis

By Geir Eide - 23 Jun, 2016 - Comments: 1

By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

A Pattern Of Success: Calibre Pattern Matching

By Mentor, a Siemens Business - 22 Jun, 2016 - Comments: 0

Calibre Pattern Matching allows you to define specific geometric configurations as visual patterns, directly from a design layout. With this visual representation, Calibre Pattern Matching opens up a whole new way to define design rules for both established and advanced nodes, and enables a wide range of innovative applications across design, verification, and test. This white paper introduces ... » read more

Pattern Matching in Design and Verification

By Michael White - 19 May, 2016 - Comments: 0

Pattern matching (PM) was first introduced as the semiconductor industry began to shift from simple one-dimensional rule checks to the two-dimensional checks required by sub-resolution lithography. These rule checks proved far more complex to write, hard to code for fast runtimes, and difficult to debug. Incorporating an automated visual capture and compare process enabled designers to define t... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?