Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models

By Alphawave Semi - 24 Apr, 2024 - Comments: 0

IBIS-AMI models have been around for a decade and evolved to provide off-chip and system designers an efficient way to assess link performance of high-speed electrical interfaces with transceivers implementing various combination of equalization techniques [1]. As with any model, for IBIS-AMI to be useful they need to be benchmarked and carefully correlated to real-world silicon performance of ... » read more

Using A Retimer To Extend Reach For PCIe 6.0 Designs

By Lou Ternullo - 10 Aug, 2023 - Comments: 0

One of the biggest changes that came with PCIe 6.0 was the transition from non-return-to-zero (NRZ) signaling to PAM4 signaling. Pulse Amplitude Modulation (PAM) enables more bits to be transmitted at the same time on a serial channel. In PCIe 6.0, this translates to 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ with 1 bit p... » read more

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications

By Cadence - 19 Jul, 2023 - Comments: 0

For nearly three decades, PCI Express® (PCIe®) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand. However, as the industry needs to evolve, so does the standard, keeping pace and driving future innovation. PCIe 6.0 is ubiquitous and offers power-efficient performance and high bandwidth for latency-sensitive appli... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation

By Synopsys - 09 May, 2023 - Comments: 0

As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe... » read more

Effective Resource Utilization In PCIe Gen6: Shared Flow Control

By Siemens EDA - 12 Apr, 2023 - Comments: 0

In PCIe 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets and applications while maintaining backward compatibility with all previous generations of PCIe. Data-intensive uses include data centers, artificial intelligence/machine learning computing, high-performance co... » read more

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications

By Cadence - 22 Mar, 2023 - Comments: 0

For nearly three decades, PCI Express (PCIe) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand. However, as the industry needs to evolve, so does the standard, keeping pace and driving future innovation. PCIe 6.0 is ubiquitous and offers power-efficient performance and high bandwidth for latency-sensitive applicati... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation

By Synopsys - 07 Mar, 2023 - Comments: 0

As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe®) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL™) and Universal Chiplet Interconnec... » read more

PCIe 6.0 Takes Data Center Performance To The Next Level

By Lou Ternullo - 12 Jan, 2023 - Comments: 0

Looking back at 2022, we saw a major update to the PCI Express (PCIe) specification. PCIe 6.0 brought with it some of the most fundamental changes yet seen by the specification, resulting in some exciting capabilities that are set to take data center performance to the next level in the years ahead. PCIe has been the interconnect of choice in computing for two decades now. Its ongoing advanc... » read more

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications

By Gary Ruggles - 19 Jul, 2022 - Comments: 0

PCIe 6.0 implementations are expandable and hierarchical with embedded switches or switch chips, allowing one root port to interface with multiple endpoints (such as storage devices, Ethernet cards, and display drivers). While the introduction of PCIe 6.0 at 64GT/s helped to increase the bandwidth available for storage applications with minimal or no increase in latency, the lack of coherency s... » read more

A Sea Change In Signaling With PCIe 6.0

By Tim Messegee - 12 May, 2022 - Comments: 0

PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

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tag: PCIe 6.0

Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models

Using A Retimer To Extend Reach For PCIe 6.0 Designs

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation

Effective Resource Utilization In PCIe Gen6: Shared Flow Control

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation

PCIe 6.0 Takes Data Center Performance To The Next Level

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications

A Sea Change In Signaling With PCIe 6.0