Server Memory: Should We Be Concerned About The Power?


After my last blog post, Server Memory: What Drives its Growth, I had a couple of people ask me, “If server memory has increased by so much in the last four years, what effect has that had on the server memory subsystem power consumption?” It’s a good question. In last month’s blog, I calculated that the maximum memory per CPU has increased from 18GB (2010, highest-end Nehalem 45nm C... » read more

Designing For Security


Some level of security is required in SoC today, whether it is in hardware, software or — most commonly — both. Of course, there is a price to pay from a power and performance perspective, but thankfully just a small one in most cases. The explosion of consumer devices has driven the need for increased security features in smart cards, smart phones, personal computers, home networks, and... » read more

Building An Efficient, Tightly-Coupled Embedded System Using An Extensible Processor


The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems. As a consequence, the power, performance and area (PPA) ratio of these systems also shifts in favor of performance at the cost of power and area... » read more

Architecture Of Data In The IoT


It’s clear that the Internet of Things (IoT) is no longer just a visionary concept. It’s on the verge of becoming a new reality. But this new reality is heavily dependent on the ability of an infrastructure to capture, secure and move data across networks. Given the tremendous amount of data that already surrounds us, this emerging paradigm will enable us to not just track and measure,... » read more

Are Processors Running Out Of Steam?


Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Tech Talk: Power, Performance And Area In 2.5D


The cost will be comparable at first, but the only way to improve power, performance AND area at the same time will be with a different architectural approach. [youtube vid=XAbE7jpjuMA] » read more

Five Emerging DRAM Interfaces You Should Know For Your Next Design


Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies— LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges. To view this white paper, click here. » read more

DDR White Paper


DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Experts At The Table: Performance Analysis


By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

Experts At The Table: Who Pays For Low Power?


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

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