The Rise Of Semiconductor IP Subsystems


The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Let’s All Meet At The Via Bar!


By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

Power Markets


There has been an ongoing discussion in the industry about the importance of power and performance and which is more important. I submit that the real question is: How much performance can be squeezed out of the power budget for any given market segment? Figure 1. Processor Market Segment Power Budgets Figure 1 shows a rough breakdown of the different market segments for processors, alo... » read more

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology


To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace. To read more, click here. » read more

Guesswork, And Other Design Paradigms


PPA for soft IP seems like an oxymoron. How do you determine the implementation characteristics (PPA — Power, Performance and Area) for something that has not yet been implemented? Flying blind until implementation would be a rookie move. More likely you are going to estimate based on a prior implementation. Not a bad approach if the IP hasn’t changed significantly and the target library is... » read more

Speed Sells


The good news is that the new iPhone battery lasts at least as long as the old one. The bad news is that Apple hasn’t offered double battery life and equivalent performance as an option for mobile users that need extended times between charges. They’re not alone, of course. At the Intel Developer Forum this week, Intel Chief Product Officer Dadi Perlmutter talked about voice and gesture-... » read more

Yikes! Why Is My SystemVerilog Testbench So Slooooow?


It turns out that [gettech id="31023" comment="SystemVerilog"] != [gettech id="31017" comment="verilog"]. OK, we all figured that out a few years ago as we started to build verification environments using [gettech id="31026" comment="IEEE 1800"] SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, ... » read more

New Challenges, New Name


As you’ll notice today, we’ve changed our name from Low Power Engineering to Low-Power/High-Performance Engineering. We don’t take name changes lightly—we've been discussing this in depth with readers, sponsors, and researchers for the past six months. The almost universal conclusion is there is a big shift underway in the semiconductor industry today, and our new logo is a better refle... » read more

FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line


The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line b... » read more

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