tag: photomasks

5nm Fab Challenges
By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Tech Talk: Double-Triple Patterning
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

Fab Tool Biz Looks Cloudy
By Mark LaPedus - 17 Dec, 2015 - Comments: 1

Amid a slowdown in the foundry and DRAM sectors, the outlook for the semiconductor equipment industry looks somewhat cloudy, if not challenging, in 2016. In fact, for equipment vendors, 2016 could resemble the lackluster year in 2015. In 2015, for example, capital spending in the foundry sector fell during the year, although NAND flash began to pick up steam. In 2015, though, the big stor... » read more

The Next Resists
By Katherine Derbyshire - 22 Oct, 2015 - Comments: 5

As EUV exposure tools, sources, and photomasks have become more capable, the lithography sector’s attention has turned to EUV photoresist. After all, once the exposure system can produce a high quality image at the wafer, the resist still has to capture it for pattern transfer. Unfortunately, the increasing emphasis on photoresist has made the limitations of current formulations even more obv... » read more

Resetting Expectations On Multi-Patterning Decomposition And Checking
By David Abercrombie - 22 Oct, 2015 - Comments: 0

It never ceases to amaze me how much confusion and misunderstanding there is when it comes to multi-patterning (MP) decomposition and checking. I sometimes forget just how new a topic it is in our industry. Because of this short-lived history, and the limited time designers have had to acquire any detailed understanding of its complexity, there appears to be some serious disconnect in expectati... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Case Studies in P&R Double-Patterning Debug
By David Abercrombie - 20 Aug, 2015 - Comments: 0

In my last article, we looked at some case studies of the unique types of issues related to double patterning (DP) that place and route (P&R) and chip finishing engineers have to deal with. I’ve got some more interesting case studies to show you this time. In modern P&R designs, the metal routes on a particular layer are unidirectional (or at least primarily unidirectional). Long p... » read more

2.5D Creeps Into SoC Designs
By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

Multiple Lithography Options Still Remain in Play
By Paula Doe - 03 Aug, 2015 - Comments: 1

The throughput and uptime of EUV, and the overlay accuracy of 193nm immersion lithography, continue to steadily improve, though neither is yet ready for 10nm production, according to speakers at SEMICON West. Mike Lercel, ASML director, Product Marketing, reported several EUV tool sites achieved 70 percent uptime for more than a week, and one customer site had done so for more than four ... » read more

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