tag: place and route

Case Studies in P&R Double-Patterning Debug
By David Abercrombie - 20 Aug, 2015 - Comments: 0

In my last article, we looked at some case studies of the unique types of issues related to double patterning (DP) that place and route (P&R) and chip finishing engineers have to deal with. I’ve got some more interesting case studies to show you this time. In modern P&R designs, the metal routes on a particular layer are unidirectional (or at least primarily unidirectional). Long p... » read more

Tear Down The Wall Between Front-End And Back-End Teams
By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation
By Mentor, a Siemens Business - 18 Jun, 2015 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To read more, click here. » read more

Case Studies In Double-Patterning Debug
By David Abercrombie - 18 Jun, 2015 - Comments: 0

Double patterning (DP) impacts just about every part of the design and manufacturing flows. However, the kinds of issues you encounter, the way they manifest themselves, and the ideal way to address them may be very different in different parts of these flows. I feel like I have spent a lot of time the last six months or so working with place and route (P&R) and chip finishing engineers on DP i... » read more

High-Level Gaps Emerge
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

It’s Time to Bring GDS “Reality” Into Routing Closure
By Jean-Marie Brunet - 17 Jul, 2014 - Comments: 0

By Nancy Nguyen and Jean-Marie Brunet Imported cells, whether macros, standard cells, or intellectual property (IP), are a common element of today’s integrated circuit (IC) designs. Historically, when designers incorporate these cells into a design, they import them using an abstract format defined by a layout exchange format (LEF) file. This abstract view provides basic information about th... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation
By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

The Week In Review: Design
By Ed Sperling - 27 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

Automatic Macro Placement for Advanced Nodes
By Various Writers - 13 Dec, 2013 - Comments: 0

Finding the best placement for macros on a modern SoC can be serious challenge to design quality and cycle time.The Olympus-SoC place and route platform offers an automated and powerful solution for automatic macro placement (AMP) that significantly reduces the iterations and cycle time required to arrive at the optimal macro configuration. This paper describes the Olympus-SoC AMP technology an... » read more

Executive Viewpoint: Atoptech’s Jue-Hsien Chern
By Brian Bailey - 13 Nov, 2013 - Comments: 0

What is the difference between skyscrapers and chips? Dr Chern has worked on both and he says it’s all about how you apply margins. Jue-Hsien Chern started his technology career earning a M.S. and B.S. in Engineering from National Taiwan University and majored in structural engineering — bridges, dams, tunnels and high-rise buildings, all of which had to withstand earthquakes. That is a ... » read more

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