Reducing SoC Power With NoCs And Caches

By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Reimagine Enterprise Data Center Design and Operations

By Cadence - 11 Sep, 2024 - Comments: 0

The Power of Digital Twin Technology This eBook showcases how large enterprises across various industries, such as aerospace, healthcare, automotive and financial services, use digital twin software to overcome unique challenges, resulting in: 30-40% reduction in power consumption and increased efficiency Extended data center lifespan and resisted cloud migration pressures Impro... » read more

Decoding Glitch Power at the RTL Stage

By Ansys - 07 Aug, 2024 - Comments: 0

In the context of analyzing digital semiconductor circuits, a glitch is any unwanted or unused signal transition, or toggle. A glitch is often a transient signal that is much shorter than a clock period and therefore is not captured by the next register stage. We also encounter full transition glitches, or transport glitches, which refer to toggles in a data path circuit that cover a full clock... » read more

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)

By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A technical paper titled “Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution” was published by researchers at ETH Zürich and Intel Corporation. This paper earned the Best Paper Award in the International Symposium on Computer Architecture (ISCA). Abstract: "Load instructions often limit instruction-level parallelism (ILP) in modern pr... » read more

KAN: Kolmogorov Arnold Networks: An Alternative To MLPs (MIT, CalTech, et al.)

By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "KAN: Kolmogorov-Arnold Networks" was published by researchers at MIT, CalTech, Northeastern University and The NSF Institute for Artificial Intelligence and Fundamental Interactions. Abstract: "Inspired by the Kolmogorov-Arnold representation theorem, we propose Kolmogorov-Arnold Networks (KANs) as promising alternatives to Multi-Layer Perceptrons (MLPs). While... » read more

Semiconductor Testing Unlocks Increasing Levels Of ADAS

By Fisher Zhang - 11 Jun, 2024 - Comments: 0

Today’s advanced driver assistance systems (ADAS) require unprecedented computing power – tasked with processing an incredible amount of data from sensors in real-time, making split-second decisions, and ensuring the safety and comfort of passengers. The challenge is fluid and, as vehicles ascend from one level of autonomous driving to the next, computational demands will rise exponentially... » read more

Efficient Electronics

By Andy Heinig - 16 May, 2024 - Comments: 0

Attention nowadays has turned to the energy consumption of systems that run on electricity. At the moment, the discussion is focused on electricity consumption in data centers: if this continues to rise at its current rate, it will account for a significant proportion of global electricity consumption in the future. Yet there are other, less visible electricity consumers whose power needs are a... » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)

By Technical Paper Link - 19 Apr, 2024 - Comments: 0

A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

The Journey To Exascale Computing And Beyond

By Steven Woo - 14 Dec, 2023 - Comments: 0

High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

Supercomputing Efficiency Lags Performance Gains

By Barry Pangrle - 30 Jun, 2023 - Comments: 0

In last month’s article, Top 500: Frontier is Still on Top, I wrote about the latest versions of the Top500 and Green500 lists. Power is an incredibly important aspect of designing a world performance leading supercomputer. (Why, I can remember back to when you could run the world’s fastest machine on only a couple MW of power.) The first Green500 list was published back in 2013. Happy 1... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?