tag: power management

Week in Review: Design, Low Power
By SE Staff - 08 Feb, 2019 - Comments: 0

The U.S. Department of Energy (DOE) has awarded $35 million for 12 projects involving ultra-efficient power management. Called Arpa-E, the program encouraged participants to use medium-voltage electricity in new ways with real-world applications, such as industry, transportation and the grid. The top two award winners were Eaton Corp. (Arden, NC) for its DC wide-bandgap static circuit breaker, ... » read more

Hidden Costs Of Shifting Left
By Brian Bailey - 26 Apr, 2018 - Comments: 0

The term "Shift Left" has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks. One such example being talked about today is the need to perform hardware/software integration much earlier in the flow, rather than leaving it as a sequ... » read more

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Got Energy?
By Grant Pierce - 10 Oct, 2016 - Comments: 0

Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem. This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Ac... » read more

Tech Talk: Micro-Architecting Power
By Ed Sperling - 07 Sep, 2016 - Comments: 0

Sonics CTO Drew Wingard talks about how to save energy on a very granular level when processing 4K video. [youtube vid=vugyCG5Y_0U] » read more

Time For A DDR Background Check
By Pat Sheridan - 28 Jul, 2016 - Comments: 0

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

Better PMIC Design Using Multi-Physics Simulation
By Karthik Srinivasan - 14 Jul, 2016 - Comments: 1

Energy efficiency and thermal management are gaining importance in the IC and system design community. Because the integrated circuit is the major source of power consumption and hence heat dissipation, semiconductor companies are under immense pressure to reduce the overall power envelope of the IC that goes into the system. This phenomenon is seen globally, irrespective of whether the chip... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

FinFET Scaling Reaches Thermal Limit
By Brian Bailey - 12 May, 2016 - Comments: 2

In 1974, Robert H. Dennard was working as an IBM researcher. He introduced the idea that MOSFETs would continue to work as voltage-controlled switches in conjunction with shrinking features, providing doping levels, the chip's geometry, and voltages are scaled along with those size reductions. This became known as Dennard's Law even though, just like Moore's Law, it was anything but a law. T... » read more

Three Common SoC Power Management Myths
By Drew Wingard - 12 May, 2016 - Comments: 0

SoCs are power-sensitive. Sometimes SoCs are sensitive because designers worry about the impact they have on the end product battery life. Sometimes designers worry about the effects of dissipating too much power on packaging and thermal issues. Sometimes designers are simply worried about the massive cooling budgets of data centers generating heat from thousands of their chips running in serve... » read more

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