tag: power

Flexibility Improves Memory Interface Bandwidth
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

In today’s SoCs, memory is the heart or at least one of the main elements of the design. As such, designing them carefully is paramount to achieving the best bandwidth, performance and power. Performance is very important to be able to access the memory and to trade and store information from different IPs with shared memories or local memories. From the power perspective, every access to... » read more

Five Emerging DRAM Interfaces You Should Know For Your Next Design
By Various Writers - 12 Sep, 2013 - Comments: 0

Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies— LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges. To view this white paper, click here. » read more

DDR White Paper
By Various Writers - 12 Sep, 2013 - Comments: 0

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more

Experts At The Table: Process Technology Challenges
By Mark LaPedus - 05 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

Memory Architectures Undergo Changes
By Ed Sperling - 22 Aug, 2013 - Comments: 0

By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 02 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

Big Iron Conundrums
By Ed Sperling - 24 May, 2013 - Comments: 0

Enormous attention is being focused on energy efficiency in mobile devices because time between charges trumps a slight boost in performance. Inside of data centers those benefits are far less clear. While energy costs remain a huge factor—they are a visible part of the bottom line costs for a CIO—how to reduce those costs is anything but a simple equation. Just adding more energy-saving... » read more

Power Markets
By Barry Pangrle - 09 May, 2013 - Comments: 0

There has been an ongoing discussion in the industry about the importance of power and performance and which is more important. I submit that the real question is: How much performance can be squeezed out of the power budget for any given market segment? Figure 1. Processor Market Segment Power Budgets Figure 1 shows a rough breakdown of the different market segments for processors, alo... » read more

The Power Problem
By Ed Sperling - 09 May, 2013 - Comments: 0

For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right. While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how perni... » read more

The Power Treadmill
By Frank Ferro - 25 Apr, 2013 - Comments: 0

By Frank Ferro The recent purchase of an LTE smart phone has me back on my power management soapbox. I upgraded my phone about a month ago to the newest version (staying with the same manufacturer as my previous device) and to my dismay, although it wasn’t completely unexpected, the battery life was actually shorter. I did not do a ‘scientific’ comparison, but following the same daily us... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy