Experts At The Table: Process Technology Challenges

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, vice president of the customer integration center at Lam Research. What follows are excerpts of that conversation.

SMD: Let’s move to the 7nm and 5nm nodes. What are the challenges of going to so-called high-mobility finFETs?
Jammy: Change is always constant, but we know how to deal with change. That’s the strength of this industry in some sense. It’s also important to identify the challenges as we go forward. From the logic space, we’ve talked about the change that is coming, which is a move to 3D structures. Moving to new materials is next, on top of all of the new materials that we’ve been adding already. We have nearly 61 elements from the periodic table getting into our chips today. Now, we’re talking about putting in germanium for the potential PFET and maybe a III-V compound for the NFET device down the road. But as you put these in, the question is how do you keep the power down? As you put these materials down, there are some critical issues that are staring at us. First, we need to make sure we put them on silicon. We are not getting away from silicon. That opens up the need for compatibility in terms of crystalline quality. The question is how do we get the right tooling, and how do we control the contamination in the fab? III-V is a dopant for silicon, and silicon is a dopant for III-V. It’s a little bit of a messy system there. But you need to be able to isolate it and have the right epi quality. You also need to go back and make an SRAM device. So, there are fundamental issues with just the manufacturing itself. The other piece of it is that once you move to germanium to some extent, but more so with III-V, you have to go back and figure out a lot of what we figured out in silicon. We have to go back and figure out contact resistance. We have to go back and understand gate stacking, and re-engineer the gate stack. And then we need to worry about etching. What do we do with all of the etch residues? So there are a number of issues and we need to peel the onion layer-by-layer. Quite a few of them are not necessarily insurmountable problems. They are mostly engineering challenges. But there is a whole list of things that I see as gaps. The industry needs to catch up to make this all successful.
Kengeri: If you take a step back and look at the guiding principals, we don’t do this for fun. We are running a business here. The industry is trying to grow and do the right things. On a very high level, the industry must adhere to one principal—PPC or power, performance and cost. We’ve got to be able to take that to the next level. Now, if you fast forward this, what are the options for 10nm, 7nm and 5nm? All of this is happening right now in the lab. So, for the next node, we are looking at many of the same things. We have PPC. We’ve already gone to 3D finFETs. There is not much we can do there. You can go with more 3D with taller fins, but there are risks there. And then we go to new materials and a few other things. We’re looking at silicon germanium, to full germanium, to III-V. We are also looking at nanowires, and that’s all at the front-end. But remember, the front-end is not enough. Even if you were to do all of these things on a device, and get the performance we are all talking about, we will still get stuck with source-drain resistance. We need to solve that problem. Back-end scaling is also a big issue. Back-end scaling has slowed down a lot more than front-end scaling. There is some visibility into front-end device scaling. But honestly, there is very little visibility on what should be done on the back end. They are all related. It’s not like you can just get the front-end device up and running. You have to have the right combination, and need to look at all of these things. So, at the front end, we are looking at gate-all-around, nanowires, silicon germanium, germanium, and III-V. Source-drain resistance is a critical piece. And then, at the back end, we are looking at better materials or going to air gaps.
Mazure: As we move forward beyond the 10nm node, say at 7nm and 5nm, we may see high-mobility materials in CMOS technologies. There will also be a series of changes to support and help this. Germanium is a perfect candidate, but there might be others. There are III-V materials, which are basically a family of materials. But not a single material is ideal or suitable for all n- or p-channel behavior. The jury is still out. Many things will happen and many things will get discovered. The industry will have to decide what’s going to be the foundation of the surface by which you will build the other materials. This will actually bring in the substrate makers, who will collaborate with the device makers to make the most appropriate choice. By then, we know we are moving towards 450mm. And by that time, germanium and III-V materials will be important. Today, to my knowledge, there is no possible way to grow bulk germanium on 450mm. So we will have to go through epitaxial technology to generate the appropriate surfaces.

SMD: What about future memory technology?
Jammy: If you switch to the memory side, there are 3D changes taking place. We are moving away from storing electrons. We are looking into a physical manifestation of resistance change. We are looking into resistance RAM. Again, that’s driven by materials. The question is how are we going to deal with these new materials and do we have an understanding of the physics? And how do we package them?

SMD: I assume the 7nm and 5nm nodes will require more process steps in the fab, right? Which processes will require the most steps?
Dixit: All of them. Cleans are a very big part of all this. This is not fully understood yet. For example, when you start putting all of these different types of materials together, there are temperature limitations and contaminates.

SMD: What else do you see from an equipment point of view?
Dixit: One thing we see today from the equipment side is that you have to start talking about variance. That is a huge factor. We spend tons of resources just on that. For example, take a 10nm line. Trying to get the same dimension and the same height with the same angle across the same layout geometries is a massive challenge. People do tricks to achieve the end result. It means that you have to pull in more resources to get that. Then, you start putting these III-V materials together. Now you are talking about various composition levels. You could be changing those as you are processing them. People are starting to look at it. So far the focus has been on the gate. There needs to be some specific thinking on what happens to source-drain, and then more so, what happens to the global interconnect? If you look at the interconnect, and then look at the ITRS roadmaps over the last 10 years, the industry put the brakes on the interconnect. The ‘k’ introduction has been de-accelerated. Today, we’re still talking about a ‘k’ value of about 2.5 and 2.7. And so, from the equipment side, we see things diverging. We don’t see one single solution for everything. From the equipment side, we used to work on one node. In the past, there used to be some time before you worked on the next node. Now, those things are happening concurrently and on a shorter time scale.

SMD: But can we afford to make all of these changes—such as 450mm, EUV, high-mobility finFETs and others—all at once?
Jammy: If you look at list of transitions taking place, I see a transition to 3D and new materials. On the architecture side, we have the SoC and SIP. Then, you have 450mm and EUV. All are happening at the same time. We need to take them in a measured fashion.