Securing AI at the Silicon Level: Solutions for a Smarter, Safer Future


This white paper explains how Synopsys Security IP embeds hardware‑rooted protection into AI SoCs and chiplets to secure their data and models. It highlights growing AI attack vectors across edge and data‑center environments and shows how technologies like PUF, tRoot HSM, interface security, and PQC create long‑term, silicon‑level trust. Why read this whitepaper: Learn how sili... » read more

IC Security Threats Spike With Quantum, AI, And Automotive


Key Takeaways: The top challenge for the chip architect is building post‑quantum cryptography securely into real hardware from the start, not just selecting approved algorithms. Security must be treated as a core silicon architecture decision early on, especially for long‑lived, automotive, and multi‑vendor systems. Automotive cybersecurity now requires a holistic approach span... » read more

Securing Hardware For The Quantum Era


Key Takeaways: Quantum threats to security are already real. Adversaries are already harvesting data that will be decrypted later by quantum computers. Quantum computers capable of breaking RSA and ECC may arrive as early as next year. Asymmetric encryption algorithms like RSA and ECC will become inadequate against quantum threats, while symmetric encryption (such as AES) is less vul... » read more

Countering Security Threats Of Quantum Attacks With PSOC Control Microcontrollers


Quantum computers of appropriate power are expected to break traditional public-key encryption such as ECC and RSA. Quantum computers that will be able to mount attacks on public-key cryptography are commonly referred to as 'Cryptographically Relevant Quantum Computers’ (CRQCs). Betting on the future existence of CRQCs, attackers may also harvest encrypted data today and to decrypt it later o... » read more

PUFs In A Post-Quantum World


With the looming threat of quantum computing on the horizon, the security landscape is changing. Explore the emerging threat and its implications for current cryptographic standards. This white paper provides an in-depth analysis of quantum computing's impact on security and explains how PUF technology can help you maintain robust security in the quantum era. Why Read This? Quantum Comp... » read more

Side-Channel Attacks On Post-Quantum Cryptography


By Mike Hamburg and Bart Stevens Device security requires designers to secure their algorithms, not only against direct attacks on the input and output, but also against side-channel attacks. This requirement is especially notable for cryptographic algorithms, since they have a regular, well-understood structure, and the secrets they process often give access to much more information. Sid... » read more

2024 Security IP Year In Review: Innovations And Best Practices


This booklet offers six insightful articles on advanced security IP technologies, helping to fortify digital systems against emerging threats. Learn about: DDR Interface Security: Defend against DRAM attacks. IoT Security: Safeguard IoT devices with SIM and Root of Trust. SRAM PUF Technology: Secure device authentication. Post-Quantum Cryptography: Protect against quantum threa... » read more

Post-Quantum Cryptography (PQC): New Algorithms For A New Era


Post-Quantum Cryptography (PQC), also known as Quantum Safe Cryptography (QSC), refers to cryptographic algorithms designed to withstand attacks by quantum computers. Quantum computers will eventually become powerful enough to break public key-based cryptography, also known as asymmetric cryptography. Public key-based cryptography is used to protect everything from your online communications... » read more

GNN-Based Pre-Silicon Power Side-Channel Analysis Framework At RTL Level


A technical paper titled “SCAR: Power Side-Channel Analysis at RTL-Level” was published by researchers at University of Texas at Dallas, Technology Innovation Institute and University of Illinois Chicago. Abstract: "Power side-channel attacks exploit the dynamic power consumption of cryptographic operations to leak sensitive information of encryption hardware. Therefore, it is necessary t... » read more

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)


A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

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