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Silicon Verified ASIC Implementation for Saber

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New research paper from Purdue University, KU Leuven, and Intel Labs titled “A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator.”

Abstract:
“National Institute of Standard & Technology (NIST) is currently running a multi-year-long standardization procedure to select quantum-safe or post-quantum cryptographic schemes to be used in the future. Saber is the only LWR based algorithm to be in the final of Round 3. This work presents a Saber ASIC which provides 1.37X power-efficient, 1.75x lower area, and 4x less memory implementation w.r.t. other SoA PQC ASIC. The energy-hungry multiplier block is 1.5x energyefficient than SoA.”

Find the technical paper here .

arXiv:2201.07375v1. Archisman Ghosh, J.M.B. Mera, Angshuman Karmakar, Debayan Das, Santosh Ghosh, Ingrid Verbauwhede, Shreyas Sen.



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