tag: Princeton University

Chip Industry’s Technical Paper Roundup: May 23
By Linda Christensen - 23 May, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=104 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits
By Technical Paper Link - 19 May, 2023 - Comments: 0

A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Chip Industry’s Technical Paper Roundup: May 16
By Linda Christensen - 16 May, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=103 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Toolbox For Designing Heterogeneous Quantum Systems
By Technical Paper Link - 08 May, 2023 - Comments: 0

A new technical paper titled "Microarchitectures for Heterogeneous Superconducting Quantum Computers" was published by researcher at: Pacific Northwest National Laboratory, Princeton University, University of Chicago, Rutgers University, MIT, Brookhaven National Laboratory, and Infleqtion. Abstract: "Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Apr, 2023 - Comments: 0

The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, ... » read more

Chip Industry’s Technical Paper Roundup: Apr. 25
By Linda Christensen - 25 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=94 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Data-Centric Reconfigurable Array Chiplets (Princeton)
By Technical Paper Link - 21 Apr, 2023 - Comments: 0

A technical paper titled "Massive Data-Centric Parallelism in the Chiplet Era" was published by researchers at Princeton University. Abstract: "Traditionally, massively parallel applications are executed on distributed systems, where computing nodes are distant enough that the parallelization schemes must minimize communication and synchronization to achieve scalability. Mapping communica... » read more

Chip Industry’s Technical Paper Roundup: Jan. 17
By Linda Christensen - 17 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library. [table id=74 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting li... » read more

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)
By Technical Paper Link - 16 Jan, 2023 - Comments: 0

A technical paper titled "Duet: Creating Harmony between Processors and Embedded FPGAs" was written by researchers at Princeton University. Abstract "The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squan... » read more

Chip Industry’s Technical Paper Roundup: Dec. 13
By Linda Christensen - 13 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week.[table id=70 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

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