tag: RAS

Strategies For Detecting Sources Of Silent Data Corruption
By Anne Meixner - 12 Mar, 2024 - Comments: 0

Engineering teams are wrestling with how to identify the root causes of silent data corruption (SDC) in a timely and cost-effective way, but the solutions are turning out to be broader and more complex than simply fixing a single defect. This is particularly vexing for data center reliability, accessibility and serviceability (RAS) engineering teams, because even the best tools and methodolo... » read more

Chip Ecosystem Apprenticeships Help Close The Talent Gap
By Liz Allan - 12 Feb, 2024 - Comments: 1

Competency-based apprenticeship programs are gaining wider acceptance across the chip industry as companies and governments look for new ways to address talent shortages, and as workers look for new skills that can span multiple industry sectors and industries. Funded in part by the CHIPS Act in the U.S. the European Chips Act, and various other nation-specific and regional programs, apprent... » read more

Risks Rise As Robotic Surgery Goes Mainstream
By John Koon - 30 Jun, 2022 - Comments: 1

As robotic-assisted surgery moves into the mainstream, so do concerns about security breaches, latency, and system performance. In the operating room, every second is critical, and technology failures or delays can be life-threatening. Robotic-assisted surgery (RAS) has around for a couple decades, but it is becoming more prevalent and significantly more complex. The technology often include... » read more

What Designers Need to Know About Error Correction Code (ECC) In DDR Memories
By Vadhiraj Sankaranarayanan - 10 Dec, 2020 - Comments: 2

As with any electronic system, errors in the memory subsystem are possible due to design failures/defects or electrical noise in any one of the components. These errors are classified as either hard-errors (caused by design failures) or soft-errors (caused by system noise or memory array bit flips due to alpha particles, etc.). To handle these memory errors during runtime, the memory subsyst... » read more

Essential DDR5 Features Designers Must Know
By Vadhiraj Sankaranarayanan - 11 Jun, 2020 - Comments: 2

JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article... » read more

Switching a Perpendicular Ferromagnetic Layer by Competing Spin Currents
By Technical Paper Link - 31 Mar, 2018 - Comments: 0

ABSTRACT "An ultimate goal of spintronics is to control magnetism via electrical means. One promising way is to utilize a current-induced spin-orbit torque (SOT) originating from the strong spin-orbit coupling in heavy metals and their interfaces to switch a single perpendicularly magnetized ferromagnetic layer at room temperature. However, experimental realization of SOT switching to date req... » read more

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