Chip Industry Week In Review


By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

For SDVs, Software Is The Biggest Challenge


Software-defined vehicles (SDVs) involve far more than just OTA applications enabling software upgrades over the air. Software that will manage hundreds of ECUs and other functions within the vehicle is expected to grow beyond hundreds of millions of lines of code, possibly making SDV software development the number one challenge in automotive design. The benefits of SDVs, such as easy updat... » read more

Auto Cyberattacks Becoming More Widespread


As vehicles become smarter, more complex, and increasingly connected, they also become more prone to cyberattacks. The challenge now is to keep pace with hackers, who are continually devising new and innovative ways to attack both software and hardware in vehicles. Recent statistics bear this out. In 2022, there was a big spike in deep/dark web activity and incidents related to application p... » read more

Why Hardware-Dependent Software Is So Critical


Hardware and software are two sides of the same coin, but they often live in different worlds. In the past, hardware and software rarely were designed together, and many companies and products failed because the total solution was unable to deliver. The big question is whether the industry has learned anything since then. At the very least, there is widespread recognition that hardware-depen... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Design, Low Power


M&A Microchip Technology acquired LegUp Computing, a provider of a high-level synthesis compiler that automatically generates high-performance FPGA hardware from software. The LegUp HLS tool will be used alongside Microchip’s VectorBlox Accelerator Software Design kit and VectorBlox Neural Networking IP generator to provide a complete front-end solution stack for C/C++ algorithm develope... » read more

Open Source Faces Challenges In 2020


I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source EDA from RTL to GDSII and 2nd WOSET Workshop on Open-Source EDA. I have also written about open-source in general, as an approach to development and an approach to business in a post from over four years ago that I think stands up well: The Paradox of Open Source. The reason I called it a paradox is that ... » read more

Week in Review: IoT, Security, Autos


Products/Services Huawei Technologies is again delaying the public introduction of its Mate X foldable smartphone. It is unlikely the product will be marketed in the U.S., given the ongoing trade war. The official rollout now seems likely to come in November, in time for the holiday shopping season. Samsung Electronics has had its problems with foldable phones, yet those were due to manufactur... » read more

Week in Review: IoT, Security, Auto


Products/Services Arm rolled out its Flexible Access program, which offers system-on-a-chip design teams the capability to try out the company’s semiconductor intellectual property, along with IP from Arm partners, before they commit to licensing IP and to pay only for what they use in production. The new engagement model is expected to prove useful for Internet of Things design projects and... » read more

Week in Review: IoT, Security, Auto


Products/Services Arteris IP reports that Bitmain licensed the Arteris Ncore Cache Coherent Interconnect intellectual property for use in its next-generation Sophon Tensor Processing Unit system-on-a-chip devices for the scalable hardware acceleration of artificial intelligence and machine learning algorithms. “Our choice of interconnect IP became more important as we continued to increase t... » read more

← Older posts