tag: RISC-V

Do Necessary Tools Exist For RISC-V Verification?
By Brian Bailey - 30 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

RISC-V Disrupting EDA
By Brian Bailey - 23 Mar, 2023 - Comments: 3

The electronic design automation (EDA) industry started in the 1980s and primarily was driven by the test and PCB industries. The test industry was focused on simulation so that test vector sets could be developed and optimized. The PCB industry needed help managing complexity as system sizes grew. That complexity soon was eclipsed by IC complexity and the costs associated with making a mist... » read more

Embedded World 2023: It’s Time To Architect All Ambitions With Custom Compute
By Lauranne Choquin - 23 Mar, 2023 - Comments: 0

As soon as we arrived in Nuremberg, we could feel the city was buzzing and ready for a great Embedded World 2023 conference. It was hard to avoid exhibitors, speakers, and visitors at breakfast in the hotel or at dinner in restaurants – not to mention the waves in the metro! It was my first time at the conference, and I found the number of attendees and the quality of discussions very satisf... » read more

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

SpGEMM Targeting RISC-V Vector Processors (Barcelona Supercomputing Center)
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "Optimization of SpGEMM with Risc-V vector instructions" was published (preprint) by researchers at the Barcelona Supercomputing Center. Abstract "The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C=A×B is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM ... » read more

What Makes RISC-V Verification Unique?
By Brian Bailey - 09 Mar, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the verification of RISC-V processors with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, senior director of alliances partner... » read more

Hardware Virtualization Support in the RISC-V CVA6 Core
By Technical Paper Link - 08 Mar, 2023 - Comments: 0

A new technical paper titled "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration" was published (preprint) by researchers at Universidade do Minho, University of Bologna, and ETH Zurich. Abstract "Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream comp... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 03 Mar, 2023 - Comments: 0

Security The Biden administration released a National Cybersecurity Strategy report this week, calling on the tech community to shoulder much more responsibility, placing "responsibility on those within our digital ecosystem that are best positioned to reduce risk and shift the consequences of poor cybersecurity away from the most vulnerable in order to make our digital ecosystem more trustwor... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy