tag: RISC-V

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. "Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on performance and energy overhe... » read more

RISC-V Open Platform for Next-Gen Automotive ECUs (ETH Zurich, Huawei)
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Towards a RISC-V Open Platform for Next-generation Automotive ECUs” was published by researchers at ETH Zurich and Huawei Research Center (Italy). Abstract: "The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses considerable challenges... » read more

Re-Targetable LLVM C/C++ Compiler For RISC-V
By Zdeněk Přikryl - 27 Jul, 2023 - Comments: 0

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are man... » read more

A Hardware Accelerator Designed For The Homomorphic SEAL-Embedded Library
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library" was published by researchers at University of Pisa. Abstract: "Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution... » read more

Megatrends At DAC
By Ann Mutschler - 17 Jul, 2023 - Comments: 0

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

Not All There: Heterogeneous Multiprocessor Design Tools
By Brian Bailey - 26 Jun, 2023 - Comments: 0

The design, implementation, and programming of multicore heterogeneous systems is becoming more common, often driven by the software workloads, but the tooling to help optimize the processors, interconnect, and memory are disjointed. Over the past few years, many tools have emerged that help with the definition and implementation of a single processor, optimized for a given set of software. ... » read more

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

The Uncertainties Of RISC-V Compliance
By Ann Mutschler - 22 Jun, 2023 - Comments: 0

How far can a RISC-V design be pushed and still be compliant? The answer isn't always black-and-white because the RISC-V concept is very different from previous open-source projects. But as interest and activity in RISC-V continues to grow, constructive discussions are taking place to address some of the challenges of designing with an open-standard ISA. “The RISC-V standard is somethin... » read more

Developing A Customized RISC-V Core For MEMS Sensors
By Tora Fridholm - 22 Jun, 2023 - Comments: 0

We recently described how Codasip Labs is working with the NimbleAI project to push the boundaries of neuromorphic vision. Let’s talk about another cool project. This project is focused on another sense, hearing. We will use our unique Codasip Studio design toolset to develop a customized RISC-V core for MEMS (micro-electro-mechanical system) sensors. Again, technology is inspired by bio... » read more

L31 Embedded Core Extensions For Wireless And Connectivity
By Codasip - 21 Jun, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G), which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable multip... » read more

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