tag: RISC-V

The Uncertainties Of RISC-V Compliance
By Ann Mutschler - 22 Jun, 2023 - Comments: 0

How far can a RISC-V design be pushed and still be compliant? The answer isn't always black-and-white because the RISC-V concept is very different from previous open-source projects. But as interest and activity in RISC-V continues to grow, constructive discussions are taking place to address some of the challenges of designing with an open-standard ISA. “The RISC-V standard is somethin... » read more

Developing A Customized RISC-V Core For MEMS Sensors
By Tora Fridholm - 22 Jun, 2023 - Comments: 0

We recently described how Codasip Labs is working with the NimbleAI project to push the boundaries of neuromorphic vision. Let’s talk about another cool project. This project is focused on another sense, hearing. We will use our unique Codasip Studio design toolset to develop a customized RISC-V core for MEMS (micro-electro-mechanical system) sensors. Again, technology is inspired by bio... » read more

L31 Embedded Core Extensions For Wireless And Connectivity
By Codasip - 21 Jun, 2023 - Comments: 0

5G is the latest generation of cellular networks using the 3rd Generation Partnership Project (3GPP) 5G New Radio air interface. Unlike previous generations of network (2G, 3G & 4G), which had a one-size-fits-all approach, 5G aims to address a wide range of very different applications. To flexibly support diverse quality of service requirements, network slicing is introduced to enable multip... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

Software-Defined Hardware Architectures
By Brian Bailey - 31 May, 2023 - Comments: 0

Hardware/software co-design has been a goal for several decades, but success has been limited. More recently, progress has been made in optimizing a processor as well as the addition of accelerators for a given software workload. While those two techniques can produce incredible gains, it is not enough. With increasing demands being placed on all types of processing, single-processor solutio... » read more

No One-Size-Fits-All Approach To RISC-V Processor Optimization
By Mike Eftimakis - 25 May, 2023 - Comments: 0

As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each application will have their own requirements, th... » read more

A Formal-Based Approach For Efficient RISC-V Processor Verification
By Codasip - 24 May, 2023 - Comments: 0

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new fu... » read more

Advanced RISC-V Verification Methodology Projects
By Imperas - 24 May, 2023 - Comments: 0

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse, and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this a... » read more

Chips Getting More Secure, But Not Quickly Enough
By Ed Sperling - 22 May, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of heterogeneous integration, more advanced RISC-V designs, and a growing awareness of security threats, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketin... » read more

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