Don’t Get Stranded On Islands, Delete Them

By Tyler Lockman - 02 Apr, 2020 - Comments: 0

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in the Allegro layout environments, but the flow for achieving this has improved significantly in recent years. Come with us, and we’ll compare what the flow u... » read more

2.5D, 3D Power Integrity

By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

Can Machine Learning Chips Help Develop Better Tools With Machine Learning?

By Vinay Patwardhan - 18 Jun, 2018 - Comments: 0

As we continue to be bombarded with AI- and machine learning-themed presentations at industry conferences, an ex-colleague told me that he is sick of seeing an outline of the human head with a processor in place of the brain. If you are a chip architect trying to build one of these data-centric architecture chips for machine learning or AI (as opposed to the compute-centric chips, which you pro... » read more

10nm And 7nm Routability – How Is Your CAD Flow Doing?

By Tobias Bjerregaard - 09 Mar, 2017 - Comments: 0

At DesignCon in January, I was a panelist at a panel session entitled “Power Integrity For 10nm/7nm SoCs - Overcoming Physical Design Challenges And TAT.” I was on the panel together with Arvind Vel, Sr. Director Applications Engineering, ANSYS, Inc. and Ruggero Castagnetti, Distinguished Engineer, Broadcom Limited. This topic is of course extremely broad, but it was interesting getting fee... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints

By John McMillan - 14 May, 2015 - Comments: 0

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

Routing Closure Challenges At 28nm And Below

By Jean-Marie Brunet - 03 Jan, 2014 - Comments: 1

As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more

Dealing With New Bottlenecks

By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

Too Many Rules

By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ed Sperling The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process. At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. Th... » read more

Routing Congestion Returns

By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Routing