tag: RRAM

Power/Performance Bits: Feb. 26
By Jesse Allen - 26 Feb, 2019 - Comments: 0

Integrated RRAM for edge AI Researchers at CEA-Leti and Stanford University have developed the first circuit integrating multiple-bit non-volatile Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. The proof-of-concept chip monolithically integrates two heterogeneous technologies: 18KB of on-chip... » read more

In-Memory Vs. Near-Memory Computing
By Mark LaPedus - 21 Feb, 2019 - Comments: 1

New memory-centric chip technologies are emerging that promise to solve the bandwidth bottleneck issues in today’s systems. The idea behind these technologies is to bring the memory closer to the processing tasks to speed up the system. This concept isn’t new and the previous versions of the technology fell short. Moreover, it’s unclear if the new approaches will live up to their billi... » read more

In-Memory Computing Challenges Come Into Focus
By Katherine Derbyshire - 06 Feb, 2019 - Comments: 6

For the last several decades, gains in computing performance have come by processing larger volumes of data more quickly and with superior precision. Memory and storage space are measured in gigabytes and terabytes now, not kilobytes and megabytes. Processors operate on 64-bit rather than 8-bit chunks of data. And yet the semiconductor industry’s ability to create and collect high quality ... » read more

Power/Performance Bits: Jan. 22
By Jesse Allen - 22 Jan, 2019 - Comments: 0

Efficient neural net training Researchers from the University of California San Diego and Adesto Technologies teamed up to improve neural network training efficiency with new hardware and algorithms that allow computation to be performed in memory. The team used an energy-efficient spiking neural network for implementing unsupervised learning in hardware. Spiking neural networks more closel... » read more

What’s the Right Path For Scaling?
By Mark LaPedus - 02 Jan, 2019 - Comments: 1

The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some option... » read more

Hybrid Memory
By Ed Sperling - 13 Sep, 2018 - Comments: 0

Gary Bronner, senior vice president of Rambus Labs, talks about the future of DRAM scaling, why one type of memory won’t solve all needs, and what the pros and cons are of different memories. https://youtu.be/R0hhDx2Fb7Q » read more

The Week In Review: Design
By Jesse Allen - 11 May, 2018 - Comments: 0

M&A IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor's parent company, S3 Group, will continue as a separate... » read more

What If We Had Bi-Directional RRAM?
By Katherine Derbyshire - 15 Feb, 2018 - Comments: 0

The ideal memristor device for neuromorphic computing would have linear and symmetric resistance behavior. Resistance would both increase and decrease gradually, allowing a direct correlation between the number of programming pulses and the resistance value. Real world RRAM devices, however, generally do not have these characteristics. In filamentary RRAM devices, the RESET operation can raise ... » read more

What’s Next In Neuromorphic Computing
By Katherine Derbyshire - 15 Feb, 2018 - Comments: 2

To integrate devices into functioning systems, it's necessary to consider what those systems are actually supposed to do. Regardless of the application, [getkc id="305" kc_name="machine learning"] tasks involve a training phase and an inference phase. In the training phase, the system is presented with a large dataset and learns how to "correctly" analyze it. In supervised learning, the data... » read more

Power/Performance Bits: July 11
By Jesse Allen - 11 Jul, 2017 - Comments: 0

3D chip integrates computing, storage Researchers at Stanford University and MIT developed a prototype 3D chip that integrates computation and data storage, based on carbon nanotubes and resistive RAM (RRAM) cells. The researchers integrated over 1 million RRAM cells and 2 million carbon nanotube FETs, making what the team says is the most complex nanoelectronic system ever made with emergi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy