tag: RTL synthesis

Achieving ISO 26262 Software Tool Confidence For Improved Automotive Functional Safety
By Synopsys - 24 Jan, 2018 - Comments: 0

Achieving ISO 26262 Software Tool Confidence for Improved Automotive Functional Safety The rapid adoption of advanced electronic systems in automobiles has prompted the automotive industry to develop the ISO 26262 functional safety standard to address the potential risks associated with failures in these systems. ISO 26262 is derived from the more general IEC 61508 standard and defines requirem... » read more

Next-Generation RTL Floorplanning
By Mentor, a Siemens Business - 10 Feb, 2016 - Comments: 0

Mentor’s physical RTL synthesis tools, including RealTime Designer and next-generation products, have the unique technology to pull placement ahead of synthesis and address the need for RTL floorplanning. Mentor’s physical RTL synthesis tools offer higher capacity, faster runtimes, optimal QoR, and physical awareness during RTL synthesis by optimizing at a higher level of abstraction and u... » read more

Mentor Buys Remainder Of Calypto
By Brian Bailey - 17 Sep, 2015 - Comments: 0

Back in 2002, a small startup company decided to tackle one of the most difficult problems in EDA—one that, if solved, could have opened up a whole new level of abstraction. Back when [getkc id="29" kc_name="logic synthesis"] was the new tool to try out, it suffered from the fact that gate-level [getkc id="11" kc_name="simulation"] had to be performed on the output, even if the input had been... » read more

How To Fix Common Power Problems
By Arvind Narayanan - 13 Aug, 2015 - Comments: 0

As the industry moves to ever more advanced technology nodes, managing power has emerged as a primary challenge in modern SoC design. With smaller nodes, the wires become taller and narrower, which increases the resistivity and leads to more pronounced voltage drop effects. Electro-migration effects are also more severe at advanced nodes, causing serious reliability concerns. Both RTL synthesis... » read more

EDA’s Clouded Future
By Brian Bailey - 25 Jun, 2015 - Comments: 0

There was a time, not that long ago, when chip design and EDA tools consumed some of the largest data centers with tens of thousands of machines and single datasets that consumed more than a hard disk could hold. The existing IT capabilities of the times were stretched to their limits. But while design sizes grew, other aspects of the flow did not develop as fast. “This has been driven by ... » read more

Can HLS Be Trusted?
By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

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