tag: RWTH Aachen University

Optimizing The Growth And Transfer Process of Graphene (Cambridge, RWTH Aachen)
By Technical Paper Link - 21 Apr, 2023 - Comments: 0

A technical paper titled "Putting High-Index Cu on the Map for High-Yield, Dry-Transferred CVD Graphene" was published by researchers at University of Cambridge, RWTH Aachen University, and National Institute for Materials Science. Abstract: "Reliable, clean transfer and interfacing of 2D material layers are technologically as important as their growth. Bringing both together remains a ch... » read more

Chip Industry’s Technical Paper Roundup: Apr. 18
By Linda Christensen - 18 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=93 /]   If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involv... » read more

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "Vertical GeSn nanowire MOSFETs for CMOS beyond silicon" was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. "Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transcon... » read more

Looking Forward To SPIE, And Beyond
By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge is not ... » read more

Chip Industry’s Technical Paper Roundup: Jan. 31
By Linda Christensen - 31 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

Wafer Scale Transfer of 2D Materials, Graphene
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A new technical paper titled "Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements" was published by researchers at Infineon Technologies AG, RWTH Aachen University, Protemics, and Advantest. Abstract "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requ... » read more

Research Bits: Jan. 17
By Jesse Allen - 17 Jan, 2023 - Comments: 0

Ionic circuit for neural nets Researchers at Harvard University and DNA Script developed an ionic circuit comprising hundreds of ionic transistors for neural net computing. While ions in water move slower than electrons in semiconductors, the team noted that the diversity of ionic species with different physical and chemical properties could be harnessed for more diverse information process... » read more

Chip Industry’s Technical Paper Roundup: Dec. 13
By Linda Christensen - 13 Dec, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week.[table id=70 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us po... » read more

Hardware Security: New Mathematical Model To Quantify Information Flow in Digital Circuits For Different Attack Models (RWTH Aachen)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A new technical paper titled "Quantitative Information Flow for Hardware: Advancing the Attack Landscape" was published by researchers at RWTH Aachen University. Abstract: "Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the security analysis is conducted by hand, l... » read more

Chip Industry’s Technical Paper Roundup: Oct 25
By Linda Christensen - 25 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=59 /] » read more

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