tag: Samsung

Week In Review: Manufacturing, Test
By Mark LaPedus - 25 Oct, 2019 - Comments: 0

Fab tools It’s been a tough period for memory. But is there now a sign of a rebound? For the September 2019 quarter, Lam Research reported revenue of $2.166 billion, and net income was $466 million, or $3.09 per diluted share on a U.S. GAAP basis. The outlook at Lam (LRCX) is a bright spot. “LRCX posted strong results and guidance, noting strength from logic and foundry in the December ... » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 18 Oct, 2019 - Comments: 0

Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Mask Making Issues With EUV
By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 11 Oct, 2019 - Comments: 0

Fab tools A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA. “APPLAUSE will focus on advanced optics, photonics and electronics packagin... » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 04 Oct, 2019 - Comments: 0

Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Scaling Battery Technology
By Jim Feldhan - 23 Sep, 2019 - Comments: 0

Batteries are an essential ingredient for the growth of electronics from small devices used for IoT as well as large batteries for electric cars. Historically, battery energy density improves 5%-8% per year. While this is much slower than the historical improvements from Moore’s Law, it’s still the kind of growth that can result in leaps in efficiency, opening the door for a better experien... » read more

Stacking Memory On Logic, Take Two
By Ed Sperling - 19 Sep, 2019 - Comments: 1

True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

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