What Works Best For Chiplets


The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various technologies and device nodes can be integrated in a single package with acceptable yield. To make this work as expected, the chip industry will have to solve a variety of well-documented technical an... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node


DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in advanced packaging. This is in addition to the previously announced $2.18 billion in funding. In a meeting next week, the U.S. and Japan are expected to cooperate on increasing semiconductor development a... » read more

AI Takes Aim At Chip Industry Workforce Training


When all the planned fabs become operational, the semiconductor industry is likely to face a worker shortage of 100,000 each in the U.S. and Europe, and more than 200,000 in Asia-Pacific, according to a McKinsey report. Since the dawn of technology, people have worried that robots, automation, and AI will steal their jobs, but these tools also can be put to use to help fill the chip industry ta... » read more

Chip Industry Week In Review


By Adam Kovac, Karen Heyman, and Liz Allan.  China introduced strict procurement guidelines aimed at blocking the use of AMD and Intel processors in government computers. Meanwhile, China urged the Netherlands to ease restrictions on deep ultraviolet (DUV) litho equipment, according to Nikkei Asia. DUV is an older technology, based on 193nm ArF lasers, but in conjunction with multi-p... » read more

Chip Industry Week In Review


By Adam Kovac, Gregory Haley, and Liz Allan. The U.S. government released a 61-page report, titled "National Strategy on Microelectronics Research,” by the Subcommittee On Microelectronics Leadership. It provides a framework for government, industry, academia, and international allies to address four major goals. Synopsys  acquired Intrinsic ID, which develops physical unclonable func... » read more

Chip Industry Week In Review


By Adam Kovac, Karen Heyman, and Liz Allan. Europe's semiconductor footprint is growing in areas that previously had little association with chips. Silicon Box plans to build a panel-level foundry in northern Italy, funded in part by the Italian government. The deal is worth around €3.2 billion ($3.6B). In addition, imec will establish a specialized 300mm chip technology pilot line in M... » read more

Chip Industry Week In Review


By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

Thinking Big: From Chips To Systems


Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

Backside Power Delivery Gears Up For 2nm Devices


The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

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