tag: Samsung

450mm And Other Emergency Measures
By Ed Sperling - 22 Sep, 2016 - Comments: 0

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

5 Takeaways From BACUS
By Mark LaPedus - 22 Sep, 2016 - Comments: 0

As usual, the recent SPIE Photomask Technology Conference, sometimes called BACUS, was a busy event. The event, which took place in San Jose, Calif., featured presentations on the usual subjects in the photomask sector. There were presentations on mask writers, inspection, metrology, repair and cleaning. And, of course, the papers included masks based on extreme ultraviolet (EUV) lithography... » read more

Grappling With Manufacturing Data
By Ed Sperling - 22 Sep, 2016 - Comments: 2

As complexity goes up with each new process node, so does the amount of data that is generated, from initial GDSII to photomasks, manufacturing, yield and post-silicon validation. But what happens to that data, and what gets shared, remain a point of contention among companies across the semiconductor ecosystem. The problem is that to speed up the entire design through manufacturing process,... » read more

Mask Maker Worries Grow
By Mark LaPedus - 22 Sep, 2016 - Comments: 0

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Sorting Out Next-Gen Memory
By Mark LaPedus - 22 Sep, 2016 - Comments: 8

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Stacked Die Changes
By Ed Sperling - 21 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 16 Sep, 2016 - Comments: 0

Chipmakers The finFET market is heating up. GlobalFoundries, Intel, Samsung and TSMC are ramping 16nm/14nm finFETs. And 10nm and 7nm finFETs are in the works. The market will shortly have a new competitor—Taiwan’s United Microelectronics Corp. (UMC). Some years ago, UMC licensed finFET technology from IBM. UMC has been a bit quiet about the 14nm finFET technology, but it has made si... » read more

7nm Market Heats Up
By Mark LaPedus - 15 Sep, 2016 - Comments: 2

The 7nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, TSMC announced plans to enter the 7nm finFET market. In addition, Intel and Samsung are also separately planning to enter the 7nm finFET race. Now, GlobalFoundries is formally announcing its 7nm finFET technology. Slated for 2018, GlobalFoundries’ 7nm fin... » read more

Stacked Die Changes
By Ed Sperling - 15 Sep, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 09 Sep, 2016 - Comments: 0

Chipmakers GlobalFoundries has rolled out its next-generation FD-SOI technology. The new 12nm FD-SOI process is called 12FDX. It is designed for a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. "Some applications require the unsurpassed performance of finFET transistors, but the vast majority of connected devices need high l... » read more

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