Technical Paper Round-Up: April 5

Neuromorphic chips, transistor defect detection, quantum, pellicles, BEV mobile charging, copper wire bonding, LrWPAN, batteries and superconductivity top the past week's technical papers. They also point to a rising level of government investment, and collaborations between schools that historically haven't worked closely together, including one that involves schools on different continents. ... » read more

Microstructural impacts on ionic conductivity of oxide solid electrolytes from a combined atomistic-mesoscale approach

Academic paper from Lawrence Livermore National Laboratory (LLNL) scientists in collaboration with San Francisco State University and the The Pennsylvania State University. Abstract "Although multiple oxide-based solid electrolyte materials with intrinsically high ionic conductivities have emerged, practical processing and synthesis routes introduce grain boundaries and other interfaces t... » read more

Less Room For Error

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more

How Many Power Islands Is Too Many?

By Ed Sperling Power domains, also known as power islands, have become to design engineers what multiple cores are to processor architects. They can serve a purpose, namely reducing static current leakage and saving battery life. But they also can add so much complexity that they can make it almost impossible to get a new chip out the door. Just as there has been talk of hundreds of cores, th... » read more