tag: scheduling

CP-Based Lot Scheduling Solutions For a Semiconductor Manufacturing (Infineon, U. of Klagenfurt)
By Technical Paper Link - 31 Mar, 2026 - Comments: 0

A new technical paper, "Quantifying the Global Impact of Constraint Programming Based Local Scheduling in Semiconductor Manufacturing," was published by Infineon and the University of Klagenfurt. Abstract "The efficiency of semiconductor frontend manufacturing highly depends on the optimization of resource allocation. In academic works, scheduling methods, i.e., based on Constraint Progra... » read more

ML for Energy-Performance-Aware Scheduling On Heterogeneous Multicore Architectures (Cambridge)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

University of Cambridge researchers published "Machine Learning for Energy-Performance-aware Scheduling." Abstract "In the post-Dennard era, optimizing embedded systems requires navigating complex trade-offs between energy efficiency and latency. Traditional heuristic tuning is often inefficient in such high-dimensional, non-smooth landscapes. In this work, we propose a Bayesian Optimizatio... » read more

Scheduling Architecture Integrated With M3D BEOL Memories For LLM Inference (Georgia Tech, Samsung)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories" was published by researchers at Georgia Institute of Technology and Samsung. Abstract "Long-context Large Language Model (LLM) inference faces increasing compute bottlenecks as attention calculations scale with context length, primarily due to t... » read more

Scheduling Multi-Model AI Workloads On Heterogeneous MCM Accelerators (UC Irvine)
By Technical Paper Link - 24 May, 2024 - Comments: 0

A technical paper titled “SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators” was published by researchers at University of California Irvine. Abstract: "Emerging multi-model workloads with heavy models like recent large language models significantly increased the compute and memory demands on hardware. To address such increasing demands, designin... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

MIT & UC Berkeley: “Exo” Programming Language Writes High Performance Code For HW Accelerators
By Technical Paper Link - 11 Jul, 2022 - Comments: 0

New research paper titled "Exocompilation for productive programming of hardware accelerators," from researchers at MIT and UC Berkeley. From their abstract: "To better support development of high-performance libraries for specialized hardware, we propose a new programming language, Exo, based on the principle of exocompilation: externalizing target-specific code generation support and op... » read more

New Approaches For Processor Architectures
By Ed Sperling - 26 Aug, 2021 - Comments: 0

Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

NN-Baton: DNN Workload Orchestration & Chiplet Granularity Exploration for Multichip Accelerators
By Technical Paper Link - 14 Jun, 2021 - Comments: 0

"Abstract—The revolution of machine learning poses an unprecedented demand for computation resources, urging more transistors on a single monolithic chip, which is not sustainable in the Post-Moore era. The multichip integration with small functional dies, called chiplets, can reduce the manufacturing cost, improve the fabrication yield, and achieve die-level reuse for different system scales... » read more

The Unexpected Impact Of Lots On Hold
By Marie Ryan - 08 Oct, 2019 - Comments: 0

One of the biggest bottlenecks in any Subcon is Lots on Hold. The problem occurs many times a week on most factory floors. It’s something you’ve grown to loathe or endure. But, is there something you can do to reduce the amount of time lots spend on hold? In this article, we will explain what Lots on Hold are and how you can make the process less painful for your team and help improve on-ti... » read more

Spreadsheets In Virtuoso
By Srinath Anantharaman - 07 Oct, 2019 - Comments: 0

The looming tape-out deadline is the nightmare that keeps most design managers up at night. Managing schedules and tracking progress is always a black art that few, if any, can master. Various project management tools and methodologies have been developed that can help, if followed diligently. However, the learning curve of the tools, or the training and overhead of the process, often result in... » read more

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