Rethinking Chip Economics

By Ed Sperling - 20 Mar, 2024 - Comments: 0

As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m... » read more

Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide (updated)

By Cycuity (Formerly Tortuga Logic) - 31 Jan, 2024 - Comments: 0

MITRE’s hardware Common Weakness Enumeration (CWE) database aggregates hardware weaknesses that are the root causes of vulnerabilities in deployed parts. In this 100+ page guide, each CWE is listed along with a Radix template Security Rule that can be filled in with design-specific signals and used as a baseline test for the respective CWE. To learn more about a specific CWE, follow the li... » read more

Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase

By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper "Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study" was published by researchers at University of Bremen, DFKI GmbH, and the German Aerospace Center. Abstract: "With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT d... » read more

RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks

By Technical Paper Link - 08 Feb, 2023 - Comments: 0

A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies

By Technical Paper Link - 11 Jan, 2023 - Comments: 0

A technical paper titled "Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations" was published by researchers at Max Planck Institute for Security and Privacy, Université catholique de Louvain (Belgium), Ruhr University Bochum, and Bundeskriminalamt. "In this work, we aim to improve upon this state of the art by presenting a... » read more

Industry Adoption Of Line-Rate Network Security Using MACsec

By Maxim Demchenko - 05 Dec, 2022 - Comments: 0

Network security protocols are the primary means of securing data in motion — that is, data communicated between closely connected physical devices, or between devices, and even virtual machines connected using a complex infrastructure. This article will explore Media Access Control security (MACsec) and how it can be used to provide foundational level network security for a wide range of app... » read more

Capture Effective Hardware Security Requirements In 3 Steps

By Cycuity (Formerly Tortuga Logic) - 05 Oct, 2022 - Comments: 0

As hardware vulnerabilities continue to rise, it’s increasingly crucial for those developing semiconductors to reduce consumer and business risk by establishing comprehensive security programs. These should include a systematic process for developing security requirements, verifying them at scale throughout the design process, and producing final documentation for security sign-off before tap... » read more

ML-Based Framework for Automatically Generating Hardware Trojan Benchmarks

By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new technical paper titled "Automatic Hardware Trojan Insertion using Machine Learning" was published by researchers at University of Florida and Stanford University. Abstract (partial): "In this paper, we present MIMIC, a novel AI-guided framework for automatic Trojan insertion, which can create a large population of valid Trojans for a given design by mimicking the properties of a small... » read more

Securing Heterogeneous Integration at the Chiplet, Interposer, and System-In-Package Levels (FICS-University of Florida)

By Technical Paper Link - 04 Aug, 2022 - Comments: 0

A new research paper titled "ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance" was published by researchers at the Florida Institute for Cybersecurity (FICS) Research, University of Florida. Abstract "The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Pa... » read more

Cybersecurity Is A Journey

By Cycuity (Formerly Tortuga Logic) - 03 Aug, 2022 - Comments: 0

Hardware Is the Foundation of Your Security Posture Due to the inability to ‘patch’ silicon, failure to identify and remediate hardware vulnerabilities early comes with catastrophic consequences. However, most of the focus and investments in cybersecurity have historically been on device software and its administrators, not on securing the underlying hardware. Hardware Vulnerabilitie... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?