tag: semiconductor test

Customizing IC Test To Improve Yield And Reliability
By Ed Sperling - 12 Sep, 2023 - Comments: 0

Testing the performance and power of semiconductors as they come off the production line is beginning to shift left in the fab, reversing a long-standing trend of assessing chips just prior to shipping. While this may sound straightforward, it's a difficult challenge which, if successful, will have broad implications for the entire design-through-manufacturing flow. Manufacturers typically g... » read more

Adding Security Into Test
By Ed Sperling - 04 Apr, 2023 - Comments: 0

Security is becoming a much bigger concern as more electronics are added into cars, as more devices are connected to the internet, and as the value of data continues to increase. The problem is that security is dynamic. It continues to change throughout the lifetime of a system, and some of these devices are expected to last for a decade or more. Lee Harrison, director of Tessent product market... » read more

Test Connections Clean Up With Real-Time Maintenance
By Anne Meixner - 08 Nov, 2022 - Comments: 0

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Testing 2.5D And 3D-ICs
By Ed Sperling - 25 Oct, 2022 - Comments: 0

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Data-driven Scheduling for High-mix and Low-volume Production in Semiconductor Assembly and Testing
By Technical Paper Link - 03 Nov, 2021 - Comments: 0

Abstract: The objective of this research is to improve scheduling decisions in high-mix low-volume (HMLV) production environments. Unique characteristics of HMLV semiconductor assembly and testing operations include: (1) Diversified Product Lines: To respond to global competition and different customer needs, manufacturers are providing diversified products to different consumers; (2) Unrelate... » read more

Total Critical Area For Optimizing Test Patterns
By Ed Sperling - 19 Oct, 2021 - Comments: 0

Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

Making Test Transparent With Better Data
By Susan Rambo - 07 Sep, 2021 - Comments: 0

Data is critical for a variety of processes inside the fab. The challenge is getting enough consistent data from different equipment and then plugging it back into the design, manufacturing, and test flows to quickly improve the process and uncover hard-to-find defective die. Progress is being made. The inspection and test industry is on the cusp of having more dynamic ways to access the dat... » read more

Designing Chips For Test Data
By Ed Sperling - 10 Aug, 2021 - Comments: 0

Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

Geo-Spatial Outlier Detection
By Anne Meixner - 19 Jul, 2021 - Comments: 0

Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

Design For Test Data
By Ed Sperling - 14 Jul, 2021 - Comments: 0

As design pushes deeper into data-driven architectures, so does test. Geir Eide, director for product management of DFT and Tessent Silicon Lifecycle Solutions at Siemens Digital Industries Software, talks with Semiconductor Engineering about a subtle but significant shift for designing testability into chips so that test data can be used at multiple stages during a device’s lifetime. » read more

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