tag: SerDes

56G 7nm SerDes: Eyewitness Account
By Mike Gianfagna - 27 Sep, 2018 - Comments: 0

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our... » read more

High-Speed SerDes At 7nm
By Ed Sperling - 30 Jul, 2018 - Comments: 0

eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

M2M’s Network Impact
By Ed Sperling - 25 Jul, 2018 - Comments: 0

Synopsys’ Manmeet Walia talks examines the impact of machine-to-machine traffic and why that requires some fundamental changes in networking architectures. Two key issues that need to be addressed are scalability and latency, which require new networking architectures. https://youtu.be/2RIQt3QVPtE » read more

5G Wireless Infrastructure Pushes High-Speed SerDes Protocols
By Mondeep Thiara - 14 Jun, 2018 - Comments: 0

5G is the 5th generation wireless system standard that, through high speeds and increased accessibility, promises to change the way we stream, communicate, work, and travel. Boasting speed capabilities of 20Gbps and network densities of 1 million connected devices per square kilometer, 5G is the required technology for the implementation of highly anticipated technologies like autonomous vehicl... » read more

The Week In Review: Design
By Jesse Allen - 01 Jun, 2018 - Comments: 0

Tools Real Intent launched Verix SimFix, an intent-driven verification solution for gate-level simulation (GLS) of digital designs designed to eliminate X-pessimism. SimFix uses mathematical methods to identify conditions under which pessimism can occur, and to determine the correct value when those conditions occur. It then generates files to use in simulation that detect and correct pessimis... » read more

Blog Review: Apr. 25
By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

Designing 5G Chips
By Ann Mutschler - 18 Apr, 2018 - Comments: 0

5G is the wireless technology of the future, and it’s coming fast. The technology boasts very high-speed data transfer rates, much lower latency than 4G LTE, and the ability to handle significantly higher densities of devices per cell site. In short, it is the best technology for the massive amount of data that will be generated by sensors in cars, IoT devices, and a growing list of next-g... » read more

Blog Review: April 4
By Jesse Allen - 04 Apr, 2018 - Comments: 0

Synopsys' Richard Solomon explains PCIe's upstream and downstream component naming and why understanding the perspective is key. Mentor's Cristian Filip dives into frequency domain analysis for high data rate SerDes links and the movement toward a simpler way of channel characterization. Cadence's Paul McLellan takes a look at the history of the RISC processors and the death of microcode ... » read more

Signal Integrity Methodology For Double-Digit Multi-Gigabit Interfaces
By Cadence - 07 Feb, 2018 - Comments: 0

As data rates for serial link interfaces such as PCI Express (PCIe) Gen 4 move into the double digits, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers. To mitigate risk and optimize designs, it is critical to move analysis as far upstream... » read more

Chiplets Gaining Steam
By Ann Mutschler - 06 Nov, 2017 - Comments: 0

Building chips from pre-verified chiplets is beginning to gain traction as a way of cutting costs and reducing time to market for heterogeneous designs. The chiplet concept has been on the drawing board for some time, but it has been viewed more as a possible future direction than a necessary solution. That perception is beginning to change as complexity rises, particularly at advanced nodes... » read more

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