The Week In Review: Design

New IP from Arm; X-pessimism; embedded vision.


Real Intent launched Verix SimFix, an intent-driven verification solution for gate-level simulation (GLS) of digital designs designed to eliminate X-pessimism. SimFix uses mathematical methods to identify conditions under which pessimism can occur, and to determine the correct value when those conditions occur. It then generates files to use in simulation that detect and correct pessimism so simulation accurately models real hardware.

Verific integrated the INVIO platform, acquired last year from Invionics, into its flagship parser platforms. INVIO is SystemVerilog- and VHDL-language agnostic and offers a high of abstraction. The integration includes the addition of C++ APIs to INVIO, and porting of Verific’s native Liberty and UPF parsers to INVIO.

Arm unveiled a new suite of IP for mobile devices, including Arm-based laptops. The suite includes the Cortex-A76 CPU with a new microarchitecture that provides a 35% increase in performance year-over-year and 40% improvement in efficiency compared to the previous generation. There’s also a new version of the Mali-G76 GPU with a focus on gaming and on-device machine learning that provides 30% higher efficiency and performance density over previous generations and the Mali-V76 VPU for UHD 8K decoding and encoding. Cadence released a 7nm Rapid Adoption Kit for the Cortex-A76 including documentation to help optimize existing digital implementation flows. Synopsys announced successful customer tapeouts of the new Arm IP using its platform, as well as a QuickStart Implementation Kit that includes scripts and reference guides for the Cortex-A76 and A55 in 7nm process.

Synopsys released a new version of its DesignWare ARC MetaWare EV Development Toolkit, an integrated programming environment for the ARC EV6x family of embedded vision processors. Additions include reduced computational, memory, and bandwidth requirements for mapping CNN graphs, support for both Caffe and Tensorflow deep-learning frameworks and CNN graphs trained with 8-bit or 12-bit precision, and advanced graph compression and runtime feature map compression/decompression capabilities.

Dolphin Integration uncorked a RISC-V MCU subsystem aimed at IoT applications. RV32 Tornado includes an adapted version of the PULP zero-riscy core from ETH-Zurich, peripherals including GPIO, UART, SPI, I2C, timers and watchdog, standard AHB/APB interfaces, an ultra-low power cache controller, and a debug unit with JTAG interface.

Kandou Bus debuted its Glasswing USR SerDes IP to enable the assembly of multiple chiplets inside a shared package without the need for interposers. The IP implements the company’s Chord signaling architecture, which is a generalization of differential signaling, and provides 500Gbps of bi-directional bandwidth on 2.4mm of die edge while consuming about 1 pJ/bit. Three test chips have been produced.

USB-IF published a new USB HID (Human Interface Device) standard for braille displays with the intent of making it easier to use a braille display across operating systems and different types of hardware, as well as removing the need for braille devices to have custom software and drivers created for a particular operating system or screen reader.

Toshiba Memory Corporation worked with Synopsys to add additional simulation algorithms to Synopsys’ FineSim Pro FastSPICE tool to address the increased design complexity of 3D NAND Flash memory, including efficient handling of massive array structures, large power distribution network, increased layout parasitic elements, and high-precision analog circuits. The additions improve simulation speed by an average of 2X, according to Synopsys.

Leave a Reply