tag: Siemens EDA

Chip Industry Week In Review
By The SE Staff - 22 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan More than 1 billion generative AI smartphones are expected be shipped during 2024 to 2027, reports Counterpoint. The share of GenAI smartphones will be 4% of the market in 2023 and is likely to double in 2024, with Samsung capturing half the market, followed by Chinese OEMs. By 2027, GenAI smartphones could account for 40% of the market. Global ... » read more

Extending Design Technology Co-Optimization From Technology Launch To HVM With Calibre Fab Solutions
By Siemens EDA - 21 Dec, 2023 - Comments: 0

As IC designs get larger and manufacturing processes get more complex, the semiconductor industry finds itself needing new solutions to prevent the propagation of systematic defects, streamline product cycle time and deliver high-quality, reliable chips. Traditionally, engineers have improved performance, power efficiency, density and cost through design-technology co-optimization (DTCO) techni... » read more

RISC-V Micro-Architectural Verification
By Brian Bailey - 21 Dec, 2023 - Comments: 3

RISC-V processors are garnering a lot of attention due to their flexibility and extensibility, but without an efficient and effective verification strategy, buggy implementations may lead to industry problems. Prior to RISC-V, processor verification almost became a lost art for most semiconductor companies. Expertise was condensed into the few commercial companies that provided processors or... » read more

Dramatic Changes Ahead For Chips And Systems
By Karen Heyman - 21 Dec, 2023 - Comments: 0

Early this year, most people had never heard of generative AI. Now the entire world is racing to capitalize on it, and that's just the beginning. New markets, such as spatial computing, quantum computing, 6G, smart infrastructure, sustainability, and many more are accelerating the need to process more data faster, more efficiently, and with much more domain specificity. Compared to the days ... » read more

2023: A Good Year For Semiconductors
By Brian Bailey - 21 Dec, 2023 - Comments: 0

Looking back, 2023 has had more than its fair share of surprises, but who were the winners and losers? The good news is that by the end of the year, almost everyone was happy. That is not how we exited 2022, where there was overcapacity, inventories had built up in many parts of the industry, and few sectors — apart from data centers — were seeing much growth. The supposed new leaders we... » read more

Extending DTCO For Today’s Competitive IC Landscape
By Le Hong - 21 Dec, 2023 - Comments: 0

As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. Designers need to accelerate d... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2023 - Comments: 0

Siemens' Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help. Cadence's Gustavo Araujo explains the various optimizations in t... » read more

Using Real Workloads To Assess Thermal Impacts
By Ann Mutschler - 14 Dec, 2023 - Comments: 0

Thermal analysis is being driven much further left in the design, fueled by demand for increased transistor density and more features on a chip or in a package, as well as the unique ways the various components may be exercised or stressed. However, getting a clear picture of the thermal activity in advanced-node chips and packages is extremely complex, and it can vary significantly by use c... » read more

Data Formats For Inference On The Edge
By Brian Bailey - 14 Dec, 2023 - Comments: 0

AI/ML training traditionally has been performed using floating point data formats, primarily because that is what was available. But this usually isn't a viable option for inference on the edge, where more compact data formats are needed to reduce area and power. Compact data formats use less space, which is important in edge devices, but the bigger concern is the power needed to move around... » read more

Achieving High-Performance, Low-Power Design Optimization With The Solido Library IP Solution
By Siemens EDA - 13 Dec, 2023 - Comments: 0

Achieving overall power, performance, and area (PPA) targets is a key goal for today’s advanced IC design projects. To accomplish this, standard cell and memory libraries must be optimized for PPA. In this white paper, we describe how the Siemens Solido IP Library Solution helps engineering teams design and verify library IP to optimize PPA tradeoffs, maximize yield, and validate for easy int... » read more

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