New Approaches To Power Decoupling

By Bryon Moyer - 24 Oct, 2024 - Comments: 0

Decoupling capacitors have long been an important aspect of maintaining a clean power source for integrated circuits, but with noise caused by rising clock frequencies, multiple power domains, and various types of advanced packaging, new approaches are needed. Power is a much more important factor than it used to be, especially in the era of AI. “Doing an AI search consumes 10X the power t... » read more

Blog Review: Oct. 23

By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

LLMs Show Promise In Secure IC Design

By Adam Kovac - 21 Oct, 2024 - Comments: 0

The introduction of large language models into the EDA flow could significantly reduce the time, effort, and cost of designing secure chips and systems, but they also could open the door to more sophisticated attacks. It's still early days for the use of LLMs in chip and system design. The technology is just beginning to be implemented, and there are numerous technical challenges that must b... » read more

Chip Industry Week In Review

By The SE Staff - 18 Oct, 2024 - Comments: 0

Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

Boost High-Performance IC Design Flows With Early Interactive Symmetry Checking

By Sara Khalaf - 17 Oct, 2024 - Comments: 0

In the realm of high-performance IC (integrated circuit) design, symmetry is not just an aesthetic preference—it’s a critical factor for ensuring proper device functionality, especially in analog and RF designs. Achieving symmetry early in the design process helps to ensure consistent electrical behavior, which is essential for meeting performance goals and maintaining device reliability. H... » read more

How Big A Deal Is Aging?

By Brian Bailey - 17 Oct, 2024 - Comments: 0

Nothing lasts forever, but in the semiconductor world things used to last long enough to become obsolete long before their end of life. That's no longer the case with newer nodes, and it is raising concerns in safety-critical markets such as automotive. Being able to fully understand what happens inside of chips is still a work in progress, and analysis approaches are trying to keep up. Unti... » read more

Unbundling Analog From Digital Where It Makes Sense

By Ed Sperling - 17 Oct, 2024 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing in analog design with the shift toward heterogeneous integration and more safety- and mission-critical applications with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom I... » read more

Mass Customization For AI Inference

By Ann Mutschler - 17 Oct, 2024 - Comments: 0

Rising complexity in AI models and an explosion in the number and variety of networks is leaving chipmakers torn between fixed-function acceleration and more programmable accelerators, and creating some novel approaches that include some of both. By all accounts, a general-purpose approach to AI processing is not meeting the grade. General-purpose processors are exactly that. They're not des... » read more

Shift Left The Design Process With Calibre Interactive Symmetry Checking

By Siemens EDA - 16 Oct, 2024 - Comments: 0

The traditional methods of symmetry checking are due for an update. The Calibre interactive, no code symmetry checking solution helps designers capture symmetry issues very early in the design cycle to reduce the number of iterations. Calibre interactive symmetry checking shifts left the whole verification process and reduces the time needed to reach tape out. What you’ll learn: Why the... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs

By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?