Chip Industry Week In Review

By The SE Staff - 08 May, 2026 - Comments: 0

Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity

By Muhammad Hassan - 07 May, 2026 - Comments: 0

By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

Next-Gen Batteries Require Impedance Data And Active Balancing

By Liz Allan - 07 May, 2026 - Comments: 0

Key Takeaways Electric vehicles and energy storage systems using LFP batteries require more sophisticated diagnostic methods because they exhibit very flat cell voltages across various charge levels, making it harder to estimate usable energy. Battery management systems are leveraging new components, AI/ML, digital twins, and other techniques to get more accurate, real-time data, includ... » read more

Using AI To Monitor Dashboards In Chips And Systems

By Ed Sperling - 06 May, 2026 - Comments: 0

Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

Designing Chips In The Context Of Rapidly Evolving AI

By Ann Mutschler - 04 May, 2026 - Comments: 0

Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

Transforming DRC Closure At Advanced Nodes

By James Paris - 30 Apr, 2026 - Comments: 0

If you’re working on SoCs at 2 nm or below, you know DRC is a different beast these days. Early in the design, it’s common for DRC runs to dump hundreds of millions—or even billions—of violations at your feet. And that’s when everything is changing fast: block interfaces aren’t fixed and constraints are shifting with every new iteration. Making sense of these massive result sets, fi... » read more

Creating Agentic EDA Methodologies

By Brian Bailey - 30 Apr, 2026 - Comments: 1

Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes

By Ann Mutschler - 30 Apr, 2026 - Comments: 0

Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Can Edge AI Keep Up?

By Ann Mutschler - 23 Apr, 2026 - Comments: 0

Key Takeaways: Model development is outpacing silicon design cycles, so edge AI architectures must prioritize adaptability. The required cadence for model updates is highly application-dependent and is closely tied to product lifetime and operational risk. Adaptability can conflict with power, performance, and area targets, so effective heterogeneous architectures and robust softwa... » read more

Blog Review: Apr. 22

By Jesse Allen - 22 Apr, 2026 - Comments: 0

In a podcast, Siemens EDA's Harry Foster and Vladislav Palfy chat about why coverage closure has become one of the biggest bottlenecks in modern verification and how a unified approach that combines planning, automation, and analytics helps teams break through coverage plateaus. Synopsys' Emily Gerken and Marc Swinnen consider the challenges of designing analog and mixed-signal circuits at a... » read more

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tag: Siemens EDA