tag: Siemens EDA

Blog Review: July 26
By Jesse Allen - 26 Jul, 2023 - Comments: 0

Siemens' Chris Spear shows how to make a group of specialized classes in SystemVerilog. Synopsys' Guy Cortez and Randy Fish consider what a silicon lifecycle management strategy looks like for SoCs deployed in HPC and data center environments. Cadence's Veena Parthan provides a primer on writing Python scripts for Fidelity, including API descriptions and different sets of packages to acce... » read more

Getting Rid Of Heat In Chips
By Brian Bailey - 20 Jul, 2023 - Comments: 1

Power consumed by semiconductors creates heat, which must be removed from the device, but how to do this efficiently is a growing challenge. Heat is the waste product of semiconductors. It is produced when power is dissipated in devices and along wires. Power is consumed when devices switch, meaning that it is dependent upon activity, and that power is constantly being wasted by imperfect de... » read more

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management
By Jeff Wilson - 20 Jul, 2023 - Comments: 0

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 19 Jul, 2023 - Comments: 0

The faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. The Calibre DesignEnhancer platform offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-clean design modifications to reduce IR drop and EM and prepare for physical verification. Not only can designers reduce EM and ... » read more

Blog Review: July 19
By Jesse Allen - 19 Jul, 2023 - Comments: 0

Siemens' Keith Felton argues that co-design-driven semiconductor package planning and prototyping is critical for design success and points to how interchange formats enable designers to make trade-off decisions for both the package and the board and communicate those recommendations back to the other design team in formats that are native to their tools. Cadence's Xin Mu explains precoding ... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 14 Jul, 2023 - Comments: 0

SEMICON West returned in force this week, with a focus on AI and deep learning  in semiconductor manufacturing, security, heterogenous ICs, and the march toward a $1 trillion chip market. Lam Research President and CEO, Tim Archer, opened with the keynote presentation. Fig. 1: SEMICON West panel: AI’s influence on growth, China-U.S. trade war, and the importance of climate policy were... » read more

Week In Review: Design, Low Power
By Susan Rambo - 14 Jul, 2023 - Comments: 0

DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

DAC/Semicon West Wednesday
By The SE Staff - 13 Jul, 2023 - Comments: 1

Trade restrictions against China were a regular topic of discussion at both DAC and Semicon West this week. Five Chinese startups exhibited prominently at this week's Design Automation Conference, in the wake of increasingly restrictive trade regulations that limit the sale of U.S. and European EDA tools used to develop advanced semiconductors. Most attendees interviewed said privately th... » read more

DAC/Semicon West Addresses Top Issues, Trends For Chips
By The SE Staff - 12 Jul, 2023 - Comments: 0

The Design Automation Conference (DAC) 2023 and Semicon West returned in full force this week, drawing in more attendees and sponsor companies than since before the pandemic. At times, booth traffic was four to five deep, blocking aisles, and standing room only was common at presentations. Hot topics included generative AI and the underlying semiconductor technology, data security, reliabili... » read more

Pinpointing Timing Delays in Complex SoCs
By Anne Meixner - 11 Jul, 2023 - Comments: 0

Telemetry circuits are becoming a necessity in complex heterogeneous chips and packages to show how these devices are behaving post-production, but fusing together relevant data to identify the sources of problems adds its own set of challenges. In the past, engineering teams could build margin into chips to offset any type of variation. But at advanced nodes and in advanced packages, tolera... » read more

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