tag: Siemens EDA

Hardware-Based Cybersecurity For Software-Defined Vehicles
By Lee Harrison - 04 May, 2023 - Comments: 0

As vehicle technology advances, so does the complexity of the electrical/electronic systems within these smart vehicles. A software-defined vehicle (SDV) relies on centralized compute and an advanced software stack to control most of its functionality, from engine performance to infotainment systems. SDVs are becoming more important as automakers look to improve vehicle performance, reduce emis... » read more

Role Of IoT Software Expanding
By John Koon - 04 May, 2023 - Comments: 0

IoT software is becoming much more sophisticated and complex as vendors seek to optimize it for specific applications, and far more essential for vendors looking to deliver devices on-time and on-budget across multiple market segments. That complexity varies widely across the IoT. For example, the sensor monitoring for a simple sprinkler system is far different than the preventive maintenanc... » read more

Automotive Safety Island
By Siemens EDA - 03 May, 2023 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. Automotive ICs, once deployed for simple functions like controlling windows, are now performing complex functions related to advanced driver-assist systems (ADAS) and autonomous driving applications. The processing power required results in very large and complex ICs that ... » read more

AI Adoption Slow For Design Tools
By Brian Bailey - 01 May, 2023 - Comments: 0

A lot of excitement, and a fair amount of hype, surrounds what artificial intelligence (AI) can do for the EDA industry. But many challenges must be overcome before AI can start designing, verifying, and implementing chips for us. Should AI replace the algorithms in use today, or does it have a different role to play? At the end of the day, AI is a technique that has strengths and weaknesses... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 28 Apr, 2023 - Comments: 0

The U.S. Commerce Department  launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on ne... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Apr, 2023 - Comments: 0

The National Institute of Standards and Technology (NIST) outlined its plan for a National Semiconductor Technology Center (NSTC) to be created using a share of the $11 billion in funds from the CHIPS Act marked for research and development. While a large portion of the CHIPS Act investment is set to boost U.S. fabs and manufacturing capabilities, the NSTC aims to also support the design side, ... » read more

EDA Makes A Frenzied Push Into Machine Learning
By Ed Sperling - 27 Apr, 2023 - Comments: 0

Machine learning is becoming a competitive prerequisite for the EDA industry. Big chipmakers are endorsing and demanding it, and most EDA companies are deploying it for one or more steps in the design flow, with plans to add much more over time. In recent weeks, the three largest EDA vendors have made sweeping announcements about incorporating ML into their tools at their respective user eve... » read more

True 3D-IC Problems
By Brian Bailey - 27 Apr, 2023 - Comments: 0

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout
By Hossam Sarhan - 27 Apr, 2023 - Comments: 0

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, wh... » read more

Pre-Layout, Post-Layout Circuit Reliability
By Siemens EDA - 26 Apr, 2023 - Comments: 0

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

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