tag: Siemens EDA

Rethinking Machine Learning For Power
By Brian Bailey - 13 Sep, 2022 - Comments: 0

The power consumed by machine learning is exploding, and while advances are being made in reducing the power consumed by them, model sizes and training sets are increasing even faster. Even with the introduction of fabrication technology advances, specialized architectures, and the application of optimization techniques, the trend is disturbing. Couple that with the explosion in edge devices... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

New Data Management Challenges
By Ann Mutschler - 13 Sep, 2022 - Comments: 0

An explosion in semiconductor design and manufacturing data, and the expanding use of chips in safety-critical and mission-critical applications, is prompting chipmakers to collect and manage that data more effectively in order to improve overall performance and reliability. This collection of data reveals a number of challenges with no simple solutions. Data may be siloed and inconsistent, ... » read more

Interactive Point-To-Point Resistance Simulations
By Siemens EDA - 12 Sep, 2022 - Comments: 0

Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

The Complex Art Of Handling S-Parameters
By Pradeep Thiagarajan - 12 Sep, 2022 - Comments: 1

By Pradeep Thiagarajan and Youssef Abdelkader IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs, and advanced packaging. Furthermore, the increasing demand for enhanced connectivity with more and faster access to data continues to drive technology towards highe... » read more

Making 5G More Reliable
By Ed Sperling - 08 Sep, 2022 - Comments: 0

The rollout of 5G is a complex and monumental effort involving multiple separate systems that need to function flawlessly together in real-time, making it difficult to determine where problems might arise, or how and when to test for them. Investments in 5G have been underway for the better part of a decade, and the technology is considered the next huge growth opportunity for mobile devices... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs
By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

The Drive Toward More Predictive Maintenance
By Anne Meixner - 08 Sep, 2022 - Comments: 0

Maintenance is a critical behind-the-scenes activity that keeps manufacturing facilities running and data centers humming. But when not performed in a timely manner, it can result in damaged products or equipment, or significant system/equipment downtime. By shifting from scheduled maintenance to predictive maintenance, factories and electronic system owners can reap substantial benefits, in... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices
By Siemens EDA - 07 Sep, 2022 - Comments: 0

Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

Challenges Mount In New Autos
By John Koon - 06 Sep, 2022 - Comments: 0

Electronics are becoming the primary differentiator for carmakers, adding an array of options that can alter everything from how a vehicle's occupants interact with their surroundings to how the vehicle drives. But the infrastructure needed to support these features also raises a slew of technology and business questions for which there are no simple answers today. For example, how will new ... » read more

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