tag: Siemens EDA

Ready, Set, Go: Outrunning Moore’s Law With 3D-IC
By Tony Mastroianni - 08 Dec, 2022 - Comments: 0

By Anthony Mastroianni and Gordon Allan, Siemens EDA 3D ICs are an exciting and promising extension of heterogeneous advanced package technology into the third dimension. Although far from mainstream, 3D IC’s time is coming, as chiplet standardization efforts and supporting tool developments begin to make 3D IC practicable and profitable to more players – big and small – and products w... » read more

IC Stresses Affect Reliability At Advanced Nodes
By Ann Mutschler - 08 Dec, 2022 - Comments: 1

Thermal-induced stress is now one of the leading causes of transistor failures, and it is becoming a top focus for chipmakers as more and different kinds of chips and materials are packaged together for safety- and mission-critical applications. The causes of stress are numerous. In heterogeneous packages, it can stem from multiple components composed of different materials. “These materia... » read more

Challenges With Adaptive Control
By Brian Bailey - 08 Dec, 2022 - Comments: 0

Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

12 Ways To Elevate Electronic Design Process Using PADS eBook
By Siemens EDA - 07 Dec, 2022 - Comments: 0

When using PADS Professional Premium, designers have access to standard PCB design functionality, such as schematic definition and physical layout, as well previously optional add-on features (now standard) and all of the latest cloud apps, including: Schematic definition: Access to everything you need: Circuit design and simulation, Component selection, library management, and signal integr... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Adopting Predictive Maintenance On Fab Tools
By Anne Meixner - 06 Dec, 2022 - Comments: 0

Predictive maintenance, based on more and better sensor data from semiconductor manufacturing equipment, can reduce downtime in the fab and ultimately cut costs compared with regularly scheduled maintenance. But implementing this approach is non-trivial, and it can be disruptive to well-honed processes and flows. Not performing maintenance quickly enough can result in damage to wafers or the... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Packetized Scan Test
By Siemens EDA - 06 Dec, 2022 - Comments: 0

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Peeling The Onion Of An Automotive IC Digital Twin
By Siemens EDA - 01 Dec, 2022 - Comments: 0

This paper defines the modern digital twin in the context of the automotive industry and as it applies to the ICs being deployed therein. Additionally, it surveys the implications arising from the need to use digital twins to connect the virtual and physical worlds for semiconductor suppliers delivering the next generation of automotive capabilities. Why should I care about digital twins? T... » read more

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