Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design

By Tarek Ramadan - 24 Feb, 2022 - Comments: 0

Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on top of a substrate (organic or silicon). Besides multiple dies, multiple substrates can typically exist in a 3D-IC assembly. In this case, the benefits of advanced packaging are taken to a whole ne... » read more

Addressing Library Characterization And Verification Challenges Using ML

By Siemens EDA - 23 Feb, 2022 - Comments: 0

At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Blog Review: Feb. 23

By Jesse Allen - 23 Feb, 2022 - Comments: 0

Synopsys' Varun Agrawal looks at four new technologies have emerged to support the demands on 5G networks and applications, the challenges in validating all of those technologies together, and what's needed to perform end-to-end testing effectively for 5G O-RAN SoCs. Siemens EDA's Ray Salemi points to how FPGA retargeting could help address supply chain difficulties and some of the challenge... » read more

Preparing For 3D-ICs

By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Improving PPA In Complex Designs With AI

By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Week In Review: Design, Low Power

By Jesse Allen - 11 Feb, 2022 - Comments: 0

Nvidia's proposed acquisition of Arm is officially off. The deal faced significant pushback from regulatory agencies in the UK, USA, and Europe, which feared it would reduce or limit competition in areas like data center. Nvidia indicated it would continue working with Arm, and it will retain a 20-year Arm license. (SoftBank will retain the $1.25 billion prepaid by Nvidia.) SoftBank said it wil... » read more

CFD Playing Increasing Role In Design

By Ann Mutschler - 10 Feb, 2022 - Comments: 0

With thermal issues and constraints increasing becoming integral concerns of electronics design, computational fluid dynamics technology is gaining traction as a way to model, analyze, predict, and ideally prevent thermal problems from materializing. From cooling a board to cooling a chip with a fan and heat sinks, all of this relies on air flow for the cooling, or the flow of liquid in some... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis

By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

Spreadsheets: Still Valuable, But More Limited

By Brian Bailey - 10 Feb, 2022 - Comments: 1

Spreadsheets have been an invaluable engineering tool for many aspects of semiconductor design and verification, but their inability to handle complexity is squeezing them out of an increasing number of applications. This is raising questions about whether they still have a role, and if so, how large that role will be. There are two sides to this issue. On one side are the users who see them... » read more

Design Challenges Increasing For Mixed-Die Packages

By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?