Week In Review: Manufacturing, Test


GlobalFoundries launched GF Labs, an “open framework of internal and external research and development initiatives that deliver a differentiated pipeline of market-driven process technology solutions for future data-centric, connected, intelligent and secure applications.” Greg Bartlett, GF's senior vice president of technology, engineering at quality, said the goal is to develop and exp... » read more

Blog Review: May 18


Coventor's Gerold Schropfer considers taking an approach from the early days of computing and using MEMS technology to create computers based on micro-scale electro-mechanical logic and memory for emerging low-energy computing applications such as autonomous sensor nodes and edge computing. Synopsys' Morten Christiansen explains how USB4 differs from USB 3.2, allowing simultaneous host-to-ho... » read more

Improving PPA With AI


AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Software-Defined Cars


Automotive architectures are becoming increasingly software-driven, a shift that simplifies upgrades and makes it easier to add new features into vehicles. All of this is enabled by the increasing digitalization of automotive functions and features, shifting from mechanical to electrical design, and increasingly from analog to digital data. That enables OEMs to add or up-sell features years ... » read more

Blog Review: May 11


Ansys' Vidyu Challa checks out how to identify the most important battery metrics for a particular application and trade these off against others with a focus on the important considerations when selecting the right battery for a consumer application, such as rechargeability, energy density, power density, shelf life, safety, form factor, cost, and flexibility. Cadence's Shyam Sharma points ... » read more

Blog Review: May 4


In a podcast, Arm's Geof Wheelwright chats with Steve Furber of the University of Manchester and Christian Mayr of Technische Universität Dresden about spiking neural networks and the SpiNNaker project to build a platform for realistic real-time models of brain functions. Synopsys' Licinio Sousa checks out how the MIPI protocol enables the connectivity needed for sensor fusion and increasin... » read more

Blog Review: April 27


Siemens' Joseph Dailey and Jake Wiltgen dispel misunderstandings around safety qualification of software tools and point to some of the safety issues that could lead to schedule delays and additional costs. Synopsys' Mark Kahan explains the testing that went into creating parts of the James Webb Space Telescope and key questions that were asked to ensure the mission could be successful even ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Synopsys uncorked its new neural processor IP, which can be used to develop scalable neural processors in automotive and consumer products. The ARC NPX6 NPU IP can run at 3,500 TOPS (30 TOPS per watt), running up to 96K MACs with enhanced utilization, new sparsity features and new interconnect for scalability. The ARC NPX6FS NPU IP and MetaWare MX Toolkit for Safety can be... » read more

Blog Review: April 20


Cadence's Paul McLellan looks at the difference between 3D packaging and 3D integration and the different approaches to system-in-package designs. Siemens' Spencer Acain finds that despite having less precision and flexibility than digital chips, analog computing is having a resurgence in the space of cutting-edge AI thanks to the speed and energy efficiency in specialized tasks. Synopsys... » read more

Automate Memory Test Through A Shared Bus Interface


The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

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