tag: Siemens

Innovative Strategies Are Improving Early Design Circuit Verification
By Raghav Katoch - 24 Sep, 2020 - Comments: 0

Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, wh... » read more

Have Processor Counts Stalled?
By Brian Bailey - 24 Sep, 2020 - Comments: 2

Survey data suggests that additional microprocessor cores are not being added into SoCs, but you have to dig into the numbers to find out what is really going on. The reasons are complicated. They include everything from software programming models to market shifts and new use cases. So while the survey numbers appear to be flat, market and technology dynamics could have a big impact in resh... » read more

New Uses For Assertions
By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Increase LVS Verification Productivity In Early Design Cycles
By Mentor, a Siemens Business - 23 Sep, 2020 - Comments: 0

With the innovative Calibre nmLVS-Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. To read more, click here. » read more

Blog Review: Sept. 23
By Jesse Allen - 23 Sep, 2020 - Comments: 0

Arm's Matthew Mattina introduces a method to reduce the cost of neural network inference by combining both low-precision representation and the complexity-reducing Winograd transform while maintaining accuracy. Cadence's Paul McLellan checks out some of the biggest machine learning systems from Nvidia, Google, and Cerebras that were presented at the recent Hot Chips. Mentor's Robin Bornof... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 18 Sep, 2020 - Comments: 0

Security Synopsys’ Software Integrity Group published the results of a security survey that looked at the ways organizations across industries are handling their software security initiatives and how to improve them. The Building Security In Maturity Model (BSIMM) version 11 (BSIMM11 Study) describes the work of 8,457 software security pros. FinTech — the technology that “follows the mon... » read more

Custom Designs, Custom Problems
By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Blog Review: Sept. 16
By Jesse Allen - 16 Sep, 2020 - Comments: 0

Cadence's Paul McLellan checks out what's new for TSMC's advanced packaging solutions and the ultra-low power, RF, eNVM, and CMOS image sensor specialty processes. Mentor's Ron Press points to an automated solution to measuring pattern value that provides a consistent, “apples to apples” assessment of patterns detecting defects based on the likelihood the physical defects occurring. S... » read more

Integrity Problems For Edge Devices
By Brian Bailey - 14 Sep, 2020 - Comments: 0

Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

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