Productivity Keeping Pace With Complexity


Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Increase LVS Verification Productivity In Early Design Cycles


With the innovative Calibre nmLVS-Recon early verification tool, designers can run targeted short isolation analysis and debugging on blocks, macros and chips in early design phases. The Calibre nmLVS-Recon short isolation use model focuses on fast, efficient, prioritized short isolation and short paths debugging. To read more, click here. » read more

Blog Review: Sept. 23


Arm's Matthew Mattina introduces a method to reduce the cost of neural network inference by combining both low-precision representation and the complexity-reducing Winograd transform while maintaining accuracy. Cadence's Paul McLellan checks out some of the biggest machine learning systems from Nvidia, Google, and Cerebras that were presented at the recent Hot Chips. Mentor's Robin Bornof... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Synopsys’ Software Integrity Group published the results of a security survey that looked at the ways organizations across industries are handling their software security initiatives and how to improve them. The Building Security In Maturity Model (BSIMM) version 11 (BSIMM11 Study) describes the work of 8,457 software security pros. FinTech — the technology that “follows the mon... » read more

Custom Designs, Custom Problems


Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Blog Review: Sept. 16


Cadence's Paul McLellan checks out what's new for TSMC's advanced packaging solutions and the ultra-low power, RF, eNVM, and CMOS image sensor specialty processes. Mentor's Ron Press points to an automated solution to measuring pattern value that provides a consistent, “apples to apples” assessment of patterns detecting defects based on the likelihood the physical defects occurring. S... » read more

Integrity Problems For Edge Devices


Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

Accelerating Simulation Of PCIe Controllers For DMA Applications


For memory-intensive and high-performance computing, direct memory access (DMA) is indispensable. A typical DMA operation in PCI Express (PCIe) entails the transfer of data from the system memory to end point devices using a point-to-point PCIe bus to reduce latency and increase memory access throughput between the CPU and the device. Verification of DMA engines is concentrated on the data t... » read more

Is DVFS Worth The Effort?


Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Dealing With Device Aging At Advanced Nodes


Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

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