Integrity Problems For Edge Devices

Noise becomes a significant issue at older nodes when voltage is significantly reduced, which is a serious issue for battery-powered devices.


Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices.

Noise can come in many forms. Some of it is static, some is dynamic.

Static noise may be due to things like process variation. “Variation is a huge issue,” says Mo Faisal, president and CEO of Movellus. “If you are running your chip near threshold, your variation from slow corner to fast is no longer 2 or 3 times. It could be up to 20 times.”

Dynamic noise comes from thermal shot noise, interference, imperfect power supplies, and many other sources. “It’s not necessarily that low voltage designs are more susceptible. It is that the noise that they are susceptible to is likely to cause the product to fail,” says Brad Griffin, product management group director for multi-physics system analysis at Cadence. “If the voltage swing is 5 volts, you have a lot of margin for noise. But if the voltage swing is 0.8 volts, you don’t have nearly as much margin.”

Analog circuitry can be more susceptible to noise than digital. “The big challenge for us is around the analog, especially that associated with wireless interfaces,” says Richard Edgar, senior director of product management at Imagination Technologies. “We have challenges on power consumption. We obviously have challenges on power leakage, and the tracks are getting so close. Also, we have inductors that are very good at causing interference to other parts of the design. We’re ending up not seeing a huge shrinkage in analog compared to what we see with the digital, because we’re actually having to keep the isolation gap nearly as wide as it would have been two or three nodes higher. Around 40nm, the shrink that we can achieve on the analog to enable us to reduce the interference around the analog circuits is constrained.”

These devices are aggressively pushing to the smaller nodes, even though they remain well behind devices found in cell phones or high-performance applications. “There are some things that are a lot worse in the newer nodes,” says Movellus’ Faisal. “One is flicker noise, which matters a lot to analog designers – especially if you are designing an amplifier or high-sensitivity circuit. Flicker noise bandwidth is growing inversely proportional to the geometry. In the past you only had to worry above a few megahertz in the older nodes, but today you have to worry about 20MHz. The bigger the noise bandwidth, the more noise energy is accumulated and therefor the worse it is to design for. New techniques will have to be invented to address these challenges if you want to do high-performance RF in advanced nodes.”

Another problem with smaller nodes is leakage current. “It is starting to dominate,” says Imagination’s Edgar. “When you should switch everything off, you still have that leakage current. Even though you’re dropping the voltages down, the leakage current is still there. We’re getting to the point, certainly for the very low-power IoT applications, where people want to shut the whole thing off more and more. Effectively the only bit you might always keep on is the PMU running inside the SoC, so it could bring the rest of the chip up.”

Even digital interfaces contain a significant amount of analog content. “Any power ripple will have a negative impact,” says Cadence’s Griffin. “We see this all the time with memory interfaces, especially with the low power versions of DDR. Those voltage swings get very small, and that’s where signal integrity tools play a key role in being able to simulate and predict the overall interaction between the power, ground and signal. You’re not dealing with the kind of problems you solved in college, where you had perfect or ideal power and ground. You’re dealing with the real world, where the signals return path is not going to be a perfect return. There are a lot of challenges.”

Adaptive systems
These challenges often lead to different ways of thinking about the problem. “Consider a system running at 0.8 volts,” says Griffin. “That means that you go from 0 to 1 around 0.4 volts, and if there’s anything that causes just a little bit of noise on the power or ground, the signal can actually switch because of that noise. That is an unwanted switch, which means your data integrity is no longer reliable. You have bit error rates. In the latest DDR interfaces, and low-power DDR interfaces, you have to qualify them with a bit error rate test. To do that, we have to simulate millions and millions of bits being transferred from point A to point B, and make sure that the number of bit errors is small enough to pass the test.”

This is where things can get really complicated. “Inside that SerDes device, there’s a lot of work going on to equalizes the signal, so that when we actually deserialize the data we’ll be able to get the right levels for ones and zeros,” says Griffin. “But what actually happens is impossible to measure. What a lot of companies do is to build a measurement device into the chip. That measurement device can send information out so you actually can see what’s happening. With information like that, a controller could make the decision that the bit error rate is increasing, perhaps because I’m not able to equalize the signal adequately, so I’m going to throttle it back to a lower data rate. That throttled back version of the interface may be able to maintain data integrity even though the performance integrity may not be maintained.”

Similar things happen with the analog interfaces. “You don’t necessarily have to be transmitting at full power,” says Edgar. “Rather than transmitting at 15 dBm, you could go down to 10 dBm. That will save power and help to manage things, but the PA is operating typically at a higher voltage than the digital. The PA is operating at 3 or 3.3 volts rather than the digital, which is down at 0.9 or 0.6 with the smaller nodes. You start to suffer from the consequence of inefficiencies. The PA is tuned to be efficient at the specific power output, and efficiency falls off on either side. Although you’re backing off, you are becoming less efficient, so you’re not really saving as much as you might assume.”

The challenge is design a device that can understand the feedback it is getting from components about data integrity or power integrity. “We can simulate all those capabilities,” says Griffin. “And then the IoT device maker can address those problems by creating the necessary monitors, creating the software or the firmware for that device, so the monitor behaves appropriately and does the right throttling.”

Changing the architecture
Many companies are having to rethink the whole architecture, not just for the IoT device itself, but also for the system it is connected to. “If we have to switch the whole chip off, we need to be able to power it back up, and you have to think about the memory,” says Edgar. “How much of it needs to be retained and where should it be retained? That might not actually be part of the IoT. It might be on the host. We’re having to change the way we think about the architecture to enable us to really power down the chip and be able to bring it up quickly.”

Another way around some of these difficulties is to transition more of the analog content into digital. “Analog circuits tend to be more sensitive to noise,” says Faisal. “If you have a circuit that is trying to generate an accurate current, then with scaling, noise is going to be higher. If the circuit is inherently switching from zero to one, you can tolerate a lot more noise. That is one of the big advantages of digital. By taking a traditional analog circuit, where you have to be aware of bias currents and voltages that are very sensitive, and doing it in digital, you now treat that like a digital solution. It becomes more immune to the noisy environment.”

This is exactly the direction that Imagination is going in. “We’re trying to see how we can move away from an analog RF to a semi-digital RF,” says Edgar. “Take the PLL, for example. We’re trying to see how we can move that out of the analog domain and into the digital domain. By moving to a semi-digital analog system, we can start to get better shrinkage. More digital PLLs are becoming available, and this will be a good start because the PLL is a considerable power consumption area. There are problems on the width of the band today. So for example, if we want this for WiFi, we need one that can work across a very wide spectrum, and we don’t really have that yet.”

Cost concerns
Size relates to cost, and cost is an important factor. “Since cost is such a big concern for IoT and edge devices, the whole product needs to be highly optimized,” says Joe Davis, product management director for Mentor, a Siemens Business. “In design, there are many ways to handle such things as environmental impact (thermal, electromagnetic, vibrational, etc.), but these techniques require area or design time, which affect the part cost. Thus, IoT design teams really need to be able to optimize the analog and digital functionality, power delivery, and reliability together to get the best over-all system cost, functionality, and reliability. It will be essential to have design tools that span both analog and digital spaces, as well as reliable physical models and verification for the fabrication processes.”

How well suited are the design tools for IoT devices? “When we’re dealing with some of the very high-end devices, such as cell phones, we expect those companies can simulate with farms of computers containing hundreds, if not thousands, of cores available to do simulations,” says Griffin. “Many IoT devices come from smaller companies, and they may not have the same level of compute technology. We have the whole multi-physics analysis tools which are, for the most part, probably more positioned for advanced companies. But in the end, the technology, the algorithms are the same. We can provide a level of performance that is good enough for the company that doesn’t have that budget to be able to run 1,000-core simulations.”

Suitable models can be hard to find. “These devices are pushing the boundaries in terms of standard cell libraries and reliability, as well as the ability to accurately model transistors,” says Faisal. “These models are required not only for the parts that you are designing, but for all of the IP that you may use. That can make it difficult for smaller companies to be able to leverage these concepts.”

While many IoT devices remain on older nodes, often having far fewer concerns about signal and power integrity, or variation, the fact that they operate on such low voltage means these are very real problems they have to deal with. In some cases, the problems are worse than for high-end devices, where design costs can be amortized across a much greater number of devices. Design teams are adapting by finding new architectures and new approaches to the problem.

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