tag: Siemens

New Architectural Issues Facing Auto Ecosystem
By Ann Mutschler - 05 Mar, 2020 - Comments: 0

As chips bound for the automotive world move to small process nodes, including 5nm and below, the automotive ecosystem is wrestling with both scaling issues and challenges related to architecting safety-critical systems using fewer chips. This may sound counterintuitive, because one of the main reasons automotive chip providers are moving to smaller nodes is to reduce the number of chips in ... » read more

The Criticality Of The E/E Architecture
By Mentor, a Siemens Business - 04 Mar, 2020 - Comments: 0

Modern vehicles are highly sophisticated systems incorporating electrical, electronic, software and mechanical components. Mechanical systems are giving way to advanced software and electronic devices, driving automakers to innovate and differentiate their vehicles via the electric and electronic (E/E) architecture. Future architectures need to be scalable across vehicle platforms, flexible to ... » read more

Blog Review: March 4
By Jesse Allen - 04 Mar, 2020 - Comments: 0

Mentor's Shivani Joshi provides a primer on design rule checks and how they can help flag potential issues in PCB design. Synopsys' Taylor Armerding argues that while better IoT security requires a change in consumer culture and habits, manufacturers and government should be doing more as well. Cadence's Johnas Street chats with several colleagues about what Black History Month means to t... » read more

Improving Circuit Reliability
By Ed Sperling - 03 Mar, 2020 - Comments: 0

Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving growing concern about the reliability and fidelity of analog circuits, and the impact of running circuits for longer periods of time under different voltage and environmental conditions. » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages
By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Feb, 2020 - Comments: 0

Tools Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys' automated debug system. Ansys released RaptorH, a tool that com... » read more

Timing Library LVF Validation For Production Design Flows
By WeiLii Tan - 27 Feb, 2020 - Comments: 3

Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

An Increasingly Complicated Relationship With Memory
By Brian Bailey - 27 Feb, 2020 - Comments: 4

The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

The Cost Of Programmability
By Brian Bailey - 27 Feb, 2020 - Comments: 1

Nothing comes for free, and that is certainly true for the programmable elements in an SoC. But without them we are left with very specific devices that can only be used for one fixed application and cannot be updated. Few complex devices are created that do not have many layers of programmability, but the sizing of those capabilities is becoming more important than in the past. There are... » read more

Parasitic Extraction of MIM/MOM Capacitors In Analog/RF Designs
By Mentor, a Siemens Business - 26 Feb, 2020 - Comments: 0

The extensive use of MIM/MOM capacitors in analog/RF designs presents designers with extraction challenges that typically require multiple extraction techniques. The Calibre xACT platform offers analog/RF designers the fast performance of a rule-based extraction engine, and the capacity and performance of a field solver, to efficiently extract all parasitic components in a timely manner, with t... » read more

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