How Secure Is Your Face?

By Yuri Nagano - 07 Nov, 2019 - Comments: 0

Biometric security, which spans everything from iris scans to fingerprint sensors, is undergoing the same kind of race against hackers as every other type of sensor. While most of these systems work well enough to identify a person, there are a number of well-known ways to defeat them. One is simply to apply newer technology to cracking algorithms used inside these devices. Improvements in p... » read more

Blog Review: Nov. 6

By Jesse Allen - 06 Nov, 2019 - Comments: 0

Cadence's Paul McLellan considers why high-performance compute, high-performance networks, and security will all be vital to the next wave of devices and the importance of optimization. Synopsys' Taylor Armerding points to some best practices for assessing your supply chain to find the weak links that could lead to a security breach, from why to make it a priority to what to ask software ven... » read more

Service Revenue Growing With Chip Complexity

By Ann Mutschler - 04 Nov, 2019 - Comments: 0

Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

Week In Review: Design, Low Power

By Jesse Allen - 01 Nov, 2019 - Comments: 0

Micron acquired FWDNXT, an AI software and hardware startup. Founded in 2017 and based in Lafayette, Indiana, FWDNXT, specializes in building machine learning deep neural network inference accelerators scalable from edge devices to server-class performance as Xilinx FPGAs, SoCs, or SDK. The company's engine already powers Micron's Deep Learning Accelerator (DLA) technology. “FWDNXT is an a... » read more

Migrating 3D Into The Mainstream

By Brian Bailey - 31 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS' Semiconductor Business Unit; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business;... » read more

Tricky Tradeoffs For LPDDR5

By Ann Mutschler - 30 Oct, 2019 - Comments: 0

LPDDR5 is slated as the next-gen memory for AI technology, autonomous driving, 5G networks, advanced displays, and leading-edge camera applications, and it is expected to compete with GDDR6 for these applications. But like all next-gen applications, balancing power, performance, and area concerns against new technology options is not straightforward. These are interesting times in the memory... » read more

Blog Review: Oct. 30

By Jesse Allen - 30 Oct, 2019 - Comments: 0

Cadence's Paul McLellan checks out the future of the automotive industry, the options for making the transition to autonomous driving, and how experience with electric vehicles influences perception of them. In a video, Mentor's Colin Walls digs into the challenges of testing memory in an embedded system. A Synopsys writer looks at doubling bandwidth in PCIe 5.0, the PHY logical changes a... » read more

Rapid Evolution For Verification Plans

By Brian Bailey - 28 Oct, 2019 - Comments: 0

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

5G Needs Cohesive Pre- And Post-Silicon Verification

By Jean-Marie Brunet - 24 Oct, 2019 - Comments: 1

While 5G doesn’t start from a clean slate, it does make significant changes to the 4G architecture. These changes mean that the ecosystem from chips to operators is evolving, giving opportunities to more companies to engage in this growing market. Realignment in fronthaul, midhaul and backhaul In particular, the radio access network (RAN) has been redefined as Cloud RAN (sometimes called ... » read more

Utilizing Computational Memory

By Brian Bailey - 24 Oct, 2019 - Comments: 0

For systems to become faster and consume less power, they must stop wasting the power required to move data around and start adding processing near memory. This approach has been proven, and products are entering the marketplace designed to fill a number of roles. Processing near memory, also known as computational memory, has been hiding in the shadows for more than a decade. Ever since the... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?