IP Management And Development At 5/3nm

By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

5G Verification Is Impossible Without Emulation

By Mentor, a Siemens Business - 23 Oct, 2019 - Comments: 0

Emulation, combined with a rich assortment of virtualized versions of the many protocols that 5G will require, is the only practical way of ensuring that the first round of silicon built will be the production version, able to handle all of the functions and configurations that it might be faced with and having the tight performance characteristics needed for successful integration into a 5G sy... » read more

Blog Review: Oct. 23

By Jesse Allen - 23 Oct, 2019 - Comments: 0

ANSYS' Magdy Abadir digs into the challenges associated with identifying and modeling electromagnetic crosstalk and the architectural and design trends that contribute to it. Cadence's Paul McLellan listens in as automotive security expert Charlie Miller points to how close we are to Level 4 autonomy and where in a car attack surfaces lie. Mentor's Brent Klingforth checks out the process ... » read more

Manufacturing Bits: Oct. 22

By Mark LaPedus - 22 Oct, 2019 - Comments: 0

3.5D chip packaging In a recent paper, PacTech has described a vertical laser assisted bonding process for use in developing advanced 3.5D chip packages. Laser assisted bonding (LAB) is an interconnection technology used in IC packaging. It uses a laser as a thermal energy, which in turn connects a die bump and a substrate pad, according to Amkor, which is the original developer of LAB tech... » read more

Week in Review: IoT, Security, Autos

By Jeff Dorsch And Susan Rambo - 18 Oct, 2019 - Comments: 0

Products/Services The Networking for Autonomous Vehicles Alliance announces that Marvell Semiconductor is joining the NAV Alliance following its acquisition of Aquantia. Fourteen companies are in the industry organization, including Bosch, Continental, Nvidia, and Volkswagen. “The NAV Alliance is developing the platforms that will create the future of transportation and we believe that Multi... » read more

Extending Portable Stimulus

By Brian Bailey - 16 Oct, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Pushing Memory Harder

By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Week in Review – IoT, Security, Autos

By Jeff Dorsch - 11 Oct, 2019 - Comments: 0

Products/Services Arm TechCon got under way with a series of announcements. Arm is a founding member of the Autonomous Vehicle Computing Consortium, along with General Motors, Toyota Motor, DENSO, Continental, Bosch, NXP Semiconductors, and Nvidia. More information on the consortium is available here. “Imagine a world where vehicles are able to perceive their dynamically changing environment... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs

By Madhur Bhargava - 10 Oct, 2019 - Comments: 0

By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

Focus Shifts To Wasted Power

By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?